Senior Lead IP Design Engineer at Advanced Micro Devices, Inc

Bangalore, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

17 Sep, 26

Salary

0.0

Posted On

19 Jun, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

RTL Design, Micro-architecture, Verilog, SystemVerilog, Cache Design, Data Fabric Architecture, PPA Optimization, Digital Design, Post Silicon Support, Coherency, Transport Architecture, SoC Requirements

Industry

Semiconductor Manufacturing

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. Senior Lead IP Design Engineer THE ROLE: As a member of the Data Fabric Team , you will help bring to life cutting-edge designs. Your role will be to micro-architect , design and deliver data fabric IP RTL components , while managing the requirements of power, performance and area , to meet next-gen fabric requirements. You will work closely with the architecture, Verification and Physical Design teams to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior architects and design engineers. The candidate will be highly detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Define Data Fabric features and capabilities required to meet SoC requirements on power, performance, Area targets Digital design implementation and micro-architecture of components of the Infinity Data Fabric, including cache design . Micro-architecture and RTL coding in Verilog/SystemVerilog . Lead design on one or more domains Work with architects and design leads to identify and assess complex technical issues Work closely with verification teams to ensure quality component development Work closely with Physical design to ensure quality PPA targets Post silicon support to ensure successful bring up PREFERRED EXPERIENCE: Excellent foundation in fabric /transport architecture and coherency Experience in memory design/cache design Experience 12+ Years in RTL Design ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR5 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Responsibilities

The role involves micro-architecting and designing data fabric IP RTL components while managing power, performance, and area targets. You will collaborate with architecture, verification, and physical design teams to ensure first-pass silicon success.