Senior Lead Physical Design Methodology Engineer at Qualcomm Technologies Inc Turkey

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

24 Dec, 25

Salary

0.0

Posted On

25 Sep, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Coding, Python, Perl, TCL, C++, Digital VLSI Implementation, STA, Power Distribution Network, EDA Tools, Primetime, ICC2, Innovus, Tempus

Industry

Telecommunications

Description

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. QCT is actively seeking candidates for VLSI Methodology and R&D positions. You will be part of the backend methodology team that develops innovative solutions for Qualcomm’s chip implementation flow. As a digital ASIC R&D Engineer, you will play a vital role in addressing challenges with Performance, Power, and Area (PPA) scaling tradeoffs to qualify technology entitlement of advance process nodes. You will be responsible for research and develop methods to improve efficiency of digital ASIC design flow and chip quality/yield. The job scope includes design automation, post-silicon debug and data mining. Required Skills Coding with Python, Perl, TCL and/or C++ Working knowledge in Digital VLSI implementation (netlist to GDS) STA Power Distribution Network (PDN) Hands on experience with EDA tools (Primetime, ICC2, Innovus, Tempus, etc.) Expected Experience: 5+ years of relevant industry experience Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

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Responsibilities

As a digital ASIC R&D Engineer, you will address challenges with Performance, Power, and Area (PPA) scaling tradeoffs. You will be responsible for research and developing methods to improve the efficiency of digital ASIC design flow and chip quality/yield.