Senior Lead -RTL Design(FEINT) Engineer at Advanced Micro Devices, Inc

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

07 Apr, 26

Salary

0.0

Posted On

07 Jan, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

RTL Design, Synthesis, Timing Analysis, Verilog, System Verilog, Perl, TCL, Makefile Scripting, Power Analysis, Low Power Optimization, CDC, RDC, LINT, ECO Implementation, VLSI Front End Design, Communication Skills

Industry

Semiconductor Manufacturing

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. Senior Lead - RTL Design Engineer THE ROLE: In this role you will be given an opportunity to work on the next generation technology that will be part of future AMD Microprocessors powering Servers and Personal Computers as well as Graphics Cards and VR sets. The UMC FEINT/Implementation team is responsible for Synthesis, Timing closure/CDC/LINT/ DFx for very high speed (>2G) design. THE PERSON: As a Synthesis design engineer, you will work with architects/designers for IP development KEY RESPONSIBILITIES: Design synthesis: Performing logical and physical synthesis of blocks in IP Design analysis: Analyzing and verifying that the design meets requirements for functionality, performance, and area Design constraints: Defining synthesis design constraints and resolving STA issues Timing analysis: Analyzing timing arc and liberty quality, and providing suggestions for fixing timing violations Design quality checks: Completing all design quality checks and data quality checks (CDC/RDC/LINT/No clock flops etc) Collaboration: Working with RTL engineers to fix timing issues Tool evaluation: Driving new tool evaluation and methodology refinement ECO Implementation :Develop/enhance auto ECO generation scripts for timing closure and ECO implementation Power: Low power optimizations/UPF PREFERRED EXPERIENCE: Synthesis engineers should have prior experience with: Synopsys tools for ASIC synthesis and timing constraints Strong background in Timing analysis and CDC Experience in CDC/RDC/LINT closure Familiar with power intent definition, implementation (UPF) Knowledge of various implementation and architectural techniques for low power optimization. Verilog and System Verilog Perl/TCL/Makefile scripting Power Analysis using Power Artist and PTPX LEC, LP signoff tools VLSI front end design steps Good communication skills and ability to work with global teams ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering and 12+ years of work experience #LI-SR5 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Responsibilities

The role involves performing logical and physical synthesis of blocks in IP and analyzing and verifying that the design meets requirements for functionality, performance, and area. Additionally, the engineer will collaborate with RTL engineers to fix timing issues and drive new tool evaluation.