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Senior Manager, Compact Modeling at Micron Technology

Hyderabad, Telangana, India -

Full Time

Start Date

Immediate

Expiry Date

24 Feb, 26

Salary

0.0

Posted On

26 Nov, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Compact Modeling, CMOS, Interconnect, Reliability, Model Development Lifecycle, Model Verification, Data Correlation, Test Structure Validation, Device Physics, PDK Development, Circuit Simulation, Mentoring, Analog Circuit Design, Memory Circuit Design, Collaboration, Technical Growth

Industry

Semiconductor Manufacturing

Description

Lead a team of engineers in the development, validation, and delivery of compact models across CMOS, interconnect, array, and reliability domains. Own and guide the complete model development lifecycle, including extraction, extrapolation, verification, and documentation. Collaborate closely with CAD, Process Integration, Design Engineering, Product Engineering, and Quality Assurance to ensure models meet performance and design enablement goals. Oversee the design and verification of test structures to support robust model development. Analyze DC and AC device data and direct advanced characterization efforts as needed to support model accuracy. Communicate model performance metrics and predictive insights to global design teams and technical leadership. Drive methodology innovation and continuous improvement in modeling workflows and tool integration. Mentor and develop technical talent, fostering a team culture centered on ownership, collaboration, and technical growth. Master's or PhD in Electrical Engineering, Physics, or a related field. 15+ years of relevant experience in the semiconductor industry, with a strong focus on compact modeling. Compact model development using tools such as BSIMPro+, IC-CAP, MBP, or equivalent. Model verification and validation through circuit simulation and data correlation. Test structure definition and validation. Delivering compact modeling collaterals as part of PDKs or design enablement flows. Strong understanding of CMOS device physics and modeling principles. Familiarity with PDK development, circuit simulators, and design environments. Demonstrated ability to mentor or manage technical teams. Experience in analog or memory circuit design is a plus.

Responsibilities

Lead a team of engineers in the development, validation, and delivery of compact models across various domains. Collaborate closely with multiple teams to ensure models meet performance and design enablement goals.