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Senior Manager Design at Infineon Technologies AG Australia
Bengaluru, karnataka, India -
Full Time

Start Date

Immediate

Expiry Date

12 Feb, 26

Salary

0.0

Posted On

14 Nov, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

No

Skills

IP Design, SoC Design, Technical Leadership, Mentoring, Processor-Based SoC Design, ARM Processors, Low-Power Architecture, High-Speed Interfaces, System Verilog, VHDL, Scripting, Communication Skills, Analytical Skills, Problem-Solving Skills, Security Architecture

Industry

Semiconductor Manufacturing

Description
Work with digital/analog/RF IP teams to arrive IP configuration at the SoC level Deliver synthesis constraints at the SoC level Participate, as applicable, in silicon debug activities. Ensure an inclusive teamwork environment, inspire team members, and role model. Work effectively with several stakeholder teams globally. B Tech with 12+ years of experience or M Tech with 10+ years of experience in IP Design with a few years of experience in SoC design Must have several years of experience in technical leadership and mentoring junior engineers. Must have expertise in processor-based SoC design, which includes (but is not limited to), ARM processors, DMAs, power/clock/reset controllers,low-power architecture, interfaces like USB/SDIO/PCIe/SPI/UART Must have a good understanding of high-speed interfaces like USB, SDIO, PCIe, and a proven track record in such developments. Expertise in System Verilog/VHDL languages Expertise with scripting Team player with good communication skills, strong analytical and problem-solving skills Familiarity with Security architecture/requirements is a plus We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills.

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Responsibilities
Work with digital/analog/RF IP teams to arrive at IP configuration at the SoC level and deliver synthesis constraints. Participate in silicon debug activities and ensure an inclusive teamwork environment while inspiring team members.