Senior ML Accelerator Modeling Engineer at WAYMO LLC

Mountain View, California, United States -

Full Time

Start Date

Immediate

Expiry Date

05 Apr, 26

Salary

259000.0

Posted On

05 Jan, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Machine Learning, Modeling, Performance Analysis, C++, Computer Architecture, Digital Logic Design, Cycle-Level Simulation, Microbenchmarks

Industry

technology;Information and Internet

Description

Waymo is an autonomous driving technology company with the mission to be the world's most trusted driver. Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the Waymo Driver—The World's Most Experienced Driver™—to improve access to mobility while saving thousands of lives now lost to traffic crashes. The Waymo Driver powers Waymo’s fully autonomous ride-hail service and can also be applied to a range of vehicle platforms and product use cases. The Waymo Driver has provided over ten million rider-only trips, enabled by its experience autonomously driving over 100 million miles on public roads and tens of billions in simulation across 15+ U.S. states. Waymo's Compute Team is tasked with a critical and exciting mission: We deliver the compute platform responsible for running the fully autonomous vehicle's software stack. To achieve our mission, we architect and create high-performance custom silicon; we develop system-level compute architectures that push the boundaries of performance, power, and latency; and we collaborate closely with many other teammates to ensure we design and optimize hardware and software for maximum performance. We are a multidisciplinary team seeking curious and talented teammates to work on one of the world's highest performance automotive compute platforms. In this hybrid role, you will report to a Hardware Engineering Manager You will: Create architectural, micro-architectural models for exploration, development and verification of machine learning accelerators Analyze workloads, define and derive representative micro-benchmarks for functional & performance goals Drive equivalence between actual hardware and simulator implementations, both for correctness and performance correlation Build scalable tools for modeling, performance analysis and optimization Interact with cross-functional engineering teams to identify opportunities and requirements You have: Bachelor's degree in Computer Science or Computer Engineering or equivalent, or equivalent practical experience 7+ years on modeling complex, high performance architectures in the industry for functionality and/or performance Experience with cycle-level simulation frameworks (SystemC, Gem5 or similar) Strong C++ programming skills and familiarity with software development methodologies Solid foundation in computer architecture and principles of digital logic design We prefer: 2+ years experience modeling high performance architectures such as CPU, GPU, NPU etc. Track record of building tools used by software and hardware teams for performance understanding and/or debug Experience writing and debugging microbenchmarks for performance correlation and correctness Excellent communication and problem solving skills #LI-Hybrid The expected base salary range for this full-time position across US locations is listed below. Actual starting pay will be based on job-related factors, including exact work location, experience, relevant training and education, and skill level. Your recruiter can share more about the specific salary range for the role location or, if the role can be performed remote, the specific salary range for your preferred location, during the hiring process. Waymo employees are also eligible to participate in Waymo’s discretionary annual bonus program, equity incentive plan, and generous Company benefits program, subject to eligibility requirements. Salary Range $204,000—$259,000 USD

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Responsibilities

You will create architectural and micro-architectural models for machine learning accelerators and analyze workloads to derive micro-benchmarks. Additionally, you will drive equivalence between hardware and simulator implementations for correctness and performance.