Senior NPU Architect at Jobgether

, , United States -

Full Time

Start Date

Immediate

Expiry Date

05 Sep, 26

Salary

240000.0

Posted On

07 Jun, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

NPU Architecture, Computer Architecture, C++, Python, Verilog, SystemVerilog, Digital Design, Microarchitecture Development, AI/ML Algorithms, Performance Analysis, Hardware Description Languages, Semiconductor Design, Generative AI, Deep Learning, Simulation Environments, Memory Orchestration

Industry

Internet Marketplace Platforms

Description

This position is listed on behalf of a partner company, who manages all applications and next steps. Our partner is looking for a Senior NPU Architect based in United States. This is an exceptional opportunity to shape the future of AI acceleration by contributing to the architecture of next-generation neural processing technologies. The role combines deep technical innovation with cross-functional collaboration, allowing you to influence both hardware and software design decisions that drive performance, scalability, and efficiency. Working alongside experienced architects, engineers, and software specialists, you will help develop advanced solutions optimized for emerging AI workloads, including large language models, diffusion models, and computer vision applications. This position offers a highly impactful environment where architectural decisions directly influence product capabilities, long-term technology strategy, and the evolution of cutting-edge AI computing platforms. \n Accountabilities: Define and develop specifications, architecture, and microarchitecture for critical processing subsystems, including compute units, memory orchestration components, and on-chip communication frameworks. Design and refine architectural features based on workload requirements, deployment workflows, and performance objectives for modern AI and machine learning applications. Build and maintain architectural models within C++ simulation environments to validate functionality, evaluate design trade-offs, and support implementation efforts. Partner closely with verification teams to establish testing strategies, validation methodologies, and infrastructure that ensure robust feature delivery. Collaborate with software engineers and fellow architects to assess system performance, identify bottlenecks, and drive optimization initiatives across hardware and software layers. Analyze emerging AI workloads, industry trends, and research developments to help guide future architectural innovations and product roadmaps. Provide technical leadership and architectural expertise throughout the development lifecycle, contributing to strategic decision-making and long-term platform evolution. Requirements: Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, Computer Engineering, or a related technical discipline with significant industry experience in architecture, semiconductor design, or AI hardware development. Ph.D. in a related field is highly valued, particularly when combined with experience in advanced processor architecture or machine learning acceleration technologies. Strong understanding of computer architecture principles, digital design methodologies, and microarchitecture development. Knowledge of AI and machine learning algorithms, frameworks, and workload characteristics, including modern generative AI and deep learning applications. Proficiency in C/C++ and Python programming for architectural modeling, simulation, and performance analysis. Experience working with hardware description languages such as Verilog or SystemVerilog. Demonstrated ability to evaluate performance, identify architectural bottlenecks, and develop innovative solutions that improve efficiency and scalability. Strong analytical thinking, problem-solving capabilities, and communication skills, with the ability to collaborate effectively across multidisciplinary engineering teams. Passion for staying current with evolving AI technologies, processor architectures, and industry advancements. Benefits: Competitive annual salary ranging from $180,000 to $240,000 USD (or $175,000 to $245,000 CAD, depending on location and experience). Fully remote work opportunity across eligible locations in the United States and Canada. Opportunity to contribute to groundbreaking innovations in AI hardware and advanced computing technologies. Exposure to highly complex technical challenges involving next-generation AI workloads and architectures. Collaborative environment with experienced architects, engineers, and technology leaders. Significant influence on product direction, architectural strategy, and future technology development. Professional growth opportunities through involvement in cutting-edge research, innovation, and large-scale system design initiatives. Competitive compensation package aligned with expertise, technical contributions, and industry experience. \n How Jobgether works: We use an AI-powered matching process to ensure your application is reviewed quickly, objectively, and fairly against the role's core requirements. Our system identifies the top-fitting candidates, and this shortlist is then shared directly with the hiring company. The final decision and next steps (interviews, assessments) are managed by their internal team. We appreciate your interest and wish you the best! Why Apply Through Jobgether? Data Privacy Notice: By submitting your application, you acknowledge that Jobgether will process your personal data to evaluate your candidacy and share relevant information with the hiring employer. This processing is based on legitimate interest and pre-contractual measures under applicable data protection laws (including GDPR). You may exercise your rights (access, rectification, erasure, objection) at any time. #LI-CL1

Responsibilities

Define and develop specifications and microarchitecture for critical NPU processing subsystems and on-chip communication frameworks. Collaborate with software and verification teams to optimize system performance and guide future architectural roadmaps for AI workloads.