MINIMUM QUALIFICATIONS

• Master’s degree in Electrical Engineering or Computer Science with a minimum of 4 years of relevant industry experience.
• In depth knowledge of hardware design courses including VLSI design, digital integrated circuits, logic design, design for testing, computer architecture, and digital design automation.
• Knowledge on physical design implementation flows, auto placement and routing (APR), static timing analysis (STA), layout design, physical design verification (PDV), IREM signoff, and CAD development.
• Experiences in research projects or internship related to RTL coding, synthesis, digital design and testing, physical implementation or design verification
• In depth knowledge of major EDA tools/design flows.
• Experience in Python/Perl/TCL language programming and CSH script.
• Ability to work regularly at a customer site in the South Bay area.

PREFERRED QUALIFICATIONS

• Able to independently complete Netlist-GDS P&R.
• Excellent communication skills and strong problem-solving skills.
• Positive, Active, Collaborative, Self-motivated, Adaptable and Flexible.
• TSMC N16 and below technology.
• Experience in software programming is a plus.

COMPANY DESCRIPTION

As a trusted technology and capacity provider, TSMC is driven by the desire to be:

• The world’s leading dedicated semiconductor foundry
• The technology leader with a strong reputation for manufacturing excellence
• Advancing semiconductor manufacturing innovations to enable the future of technology

TSMC pioneered the pure-play foundry business model when it was founded in 1987 and has been the world’s leading dedicated semiconductor foundry ever since. The Company supports a thriving ecosystem of global customers and partners with the industry’s leading process technologies and a portfolio of design enablement solutions to unleash innovation for the global semiconductor industry. With global operations spanning Asia, Europe, and North America, TSMC serves as a committed corporate citizen around the world. In North America, TSMC has a strong sales and service organization that works with customers by helping them achieve silicon success with cutting-edge technologies and manufacturing excellence. The Company has continued to accelerate its R&D investment and staffing in recent years and is expanding its manufacturing footprint to support customer innovation with 3D IC technologies and optimal manufacturing capacity.

OVERVIEW OF ROLE

As a Senior Physical Design Engineer, you will be responsible for the physical design implementation PnR run, Performance/Power/Area (PPA) comparison, congestion & DRC analysis, and design optimization. You may also do synthesis, debugging & data analysis, scripting, STA or timing analysis. You will be reporting to Manager of Advanced Chip implementation team at its San Jose Design Center, California and joining a team of engineers dedicated to pushing the envelope for the world’s leading semiconductor company. We are currently operating in a hybrid work schedule with 4 days in office.

RESPONSIBILITIES

• Responsible for the physical implementation on TSMC’s most advanced process nodes.
• Netlist-to-GDS flow including block/soc-level placement, clock tree synthesis, routing, and design optimization.
• Evaluate flow and methodologies to optimize power, performance, and area (PPA).
• Analyze standard cell library utilization and route congestion data.
• CAD development including customizing design flows and creating comparison tables using scripting language such as TCL, Python, Perl and Shell.