ABOUT THE JOB YOU’RE CONSIDERING

• Develop block-level and SoC-level timing constraints, and drive full-chip STA setup and signoff for multi-corner, multi-voltage designs.
• Own the timing flow and execution to meet SoC timing goals, including timing budgeting, repeater planning, and the generation and management of constraints and exceptions.
• Collaborate closely with block and SoC design teams to understand design requirements, STA constraints, and convergence challenges.
• Work in tandem with physical implementation teams to ensure designs meet QoR targets and assist in debugging timing failures.

YOUR SKILLS AND EXPERIENCE

• 10+ years of professional experience in ASIC implementation and CAD methodology, with a strong preference for experience in timing closure of high-performance designs.
• Proven expertise in STA constraint generation, timing analysis, convergence, and ECO implementation at both block and full-chip levels.
• Solid experience with multi-voltage design implementation; experience in STA closure for low-power and multi-power mode designs is a strong plus.
• Proficiency with industry-standard ASIC EDA tools, especially Synopsys Design Compiler and PrimeTime.
• Strong scripting skills in languages such as TCL, Perl, and/or Python.
• Experience in developing scripts to automate design flows and analysis tasks.
• Hands-on experience with physical design implementation is a plus.
• Excellent communication skills, with the ability to manage multiple projects and collaborate with geographically distributed teams.
• Strong analytical and problem-solving abilities, with meticulous attention to detail.

• Develop block and SoC timing constraints, and perform full-chip STA setup and signoff for multi-corner, multi-voltage designs.
• Own the timing flow and execution to meet SoC timing requirements, including budgeting, repeater planning, and managing constraints/exceptions.
• Collaborate with design teams to understand STA constraints and convergence challenges.
• Partner with physical implementation teams to ensure QoR targets are met and assist in debugging timing issues.