Senior Physical Design Engineer -PnR implementation. at Advanced Micro Devices, Inc

Hyderabad, Telangana, India -

Full Time

Start Date

Immediate

Expiry Date

13 Sep, 26

Salary

0.0

Posted On

15 Jun, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Physical Verification, PnR Implementation, DRC, ERC, LVS, DFM, Antenna, PERC, Calibre, IO Planning, Bump Planning, RDL Generation, SOC Design, Digital IP, Sign-off Flow

Industry

Semiconductor Manufacturing

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. SMTS SILICON DESIGN ENGINEER Excellent understanding of Physical Verification flow with in-depth experience in analyzing and debugging DRC, ERC, LVS, DFM, Antenna, PERC (Mostly Working on Calibre tool) Experience in IO, Bump planning and fullchip RDL generation for Power & IO/Signals Work on physical verification (DRC/LVS) of state-of-the-art SOCs/digital IPs/blocks at cutting edge technology nodes of various foundries. Work hands-on to solve critical design and execution issues related to physical verification and sign-off Strong Technical problem and debugging solving. Own physical verification and sign-off flows, methodologies and execution of SoCs #LI-PK2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Responsibilities

The role involves owning physical verification and sign-off flows for state-of-the-art SOCs and digital IPs. Key tasks include analyzing and debugging DRC, LVS, and DFM issues while managing IO and bump planning.