Senior Principal Analog Design Engineer at PowerLattice Technologies Inc

Vancouver, Washington, United States -

Full Time

Start Date

Immediate

Expiry Date

30 May, 26

Salary

0.0

Posted On

01 Mar, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Analog Design, Mixed-Signal, SoC Development, Architecture Definition, Silicon Validation, Technical Leadership, Feasibility Analysis, Bandgap References, Oscillators, LDOs, Opamps, ADCs, DACs, Schematic Design, Layout Guidance, Post-Layout Simulations

Industry

Semiconductor Manufacturing

Description

Hybrid requiring 3 days a week onsite in the office Reports To: Head of Engineering About Us PowerLattice is a well-funded semiconductor start-up company backed by well-known large Silicon Valley VCs. The company is working on the industry’s groundbreaking chiplet solution for a fundamental shift in how high-performance chips get powered, paving the way for the next generation of AI and advanced computing. About the Role We are seeking a highly experienced Senior Principal Analog IC Design Engineer to serve a leadership role for advanced mixed-signal / analog SoC developments. This individual will provide technical leadership from architecture definition through silicon validation and production ramp. The ideal candidate combines deep analog design expertise with strong cross-functional leadership skills and a proven record of accomplishment of delivering complex ICs to market. Key Responsibilities About the Role Define and drive overall chip architecture and top-level specifications. Lead analog and mixed-signal block partitioning and system integration. Perform high-level feasibility analysis and risk assessment. Review and approve block-level designs to ensure architectural alignment. Drive silicon bring-up strategy and debug execution. Architect and design high-performance analog blocks such as Bandgap references, Oscillators, LDOs, Opamps, ADCs, or DAC. Perform circuit design starting with initial block-level specifications. Conduct schematic design, simulation, and optimization to meet performance targets. Provide layout guidance and collaborate closely with layout engineers to ensure design intent is met. Perform post-layout simulations (PEX) and correlation with pre-layout results. Participate in design reviews and contribute to design documentation. Post silicon works for block level evaluation, characterization, and debugging. Follow best practices for analog IC design, verification, and signoff. Minimum Qualifications M.S. or Ph.D. in electrical engineering or related fields. 15+ years of hands-on analog IC design experience. Proven experience as a technical lead or chip lead on successful tapeouts. Strong expertise in CMOS analog design fundamentals. Deep understanding of noise, linearity, stability, and precision design. Experience with advanced CMOS nodes. Strong knowledge of ESD, reliability, and production considerations. Demonstrated leadership and mentorship capabilities. Preferred Qualifications Experience in deep submicron CMOS technologies. Familiarity with high power, high accuracy analog design techniques. Good communication skills and ability to work in a collaborative team environment. Compensation & Benefits Competitive salary and stock option grant Comprehensive benefits package including health, dental, vision, and 401(k)

Responsibilities

This role involves defining and driving the overall chip architecture and top-level specifications, leading analog and mixed-signal block partitioning, and overseeing system integration. Key duties include architecting high-performance analog blocks, performing circuit design, simulation, optimization, and driving the silicon bring-up and debug execution.