Senior Principal CPU Architect at Huawei Technologies Greece

Cambridge, England, United Kingdom -

Full Time

Start Date

Immediate

Expiry Date

20 Sep, 26

Salary

0.0

Posted On

22 Jun, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

CPU Architecture, ISA Definition, Out-of-Order Execution, Cycle-Accurate Modeling, Hardware/Software Co-Design, Workload Profiling, C++, Python, ARM, x86, RISC-V, Cache Hierarchies, Branch Prediction, Speculative Execution, PPA Analysis, LLVM/GCC

Industry

Telecommunications

Description

About Huawei Research and Development UK Limited Founded in 1987, Huawei is a leading global provider of information and communications technology (ICT) infrastructure and smart devices. We have 207,000 employees and operate in over 170 countries and regions, serving more than three billion people around the world. Our vision and mission is to bring digital to every person, home and organization for a fully connected, intelligent world. To this end, we will drive ubiquitous connectivity and promote equal access to networks; bring cloud and artificial intelligence to all four corners of the earth to provide superior computing power where you need it, when you need it; build digital platforms to help all industries and organizations become more agile, efficient, and dynamic; redefine user experience with AI, making it more personalized for people in all aspects of their life, whether they’re at home, in the office, or on the go. This spirit of innovation has led Huawei to work in close partnership with leading academic institutions in the UK to develop and refine the latest technologies. With a shared commitment to innovation and progress, both parties have worked together to achieve common goals and establish a strong partnership. The partnership between UK and Huawei help to develop the technologies of the future that will transform the way we all communicate, work and live. For the past 30 years we have maintained an unwavering focus, rejecting shortcuts and easy opportunities that don't align with our core business. With a practical approach to everything we do, we concentrate our efforts and invest patiently to drive technological breakthroughs. This strategic focus is a reflection of our core values: Staying customer-centric, Inspiring dedication, Persevering, Growing by reflection. Huawei Research and Development UK Limited Overview Huawei’s vision is a fully connected, intelligent world. To achieve this, we work to inspire passion for basic research around the world. Our combined passion drives development across the global innovation value chain. Huawei has the largest Research and Development organization in the world with 96,000+ employees in research centers around the globe. In the UK, we already have design centers in Cambridge, London, Edinburgh and Ipswich. We continue to explore and define new research directions and new services. We have expanded our collaborations with academic researchers; researched new network architectures, integration of communications and key enabling technologies; and developed the fundamental theories of these technologies. We invite you to join us on this exciting journey and drive your career forward. Job Summary We are seeking a visionary and technically accomplished Senior Principal CPU Architect based in Cambridge, England, to lead the definition, modeling, and co-design of our next-generation (N+1) and future-generation (N+2) high-performance CPU architectures. In this highly strategic role, you will bridge the gap between evolving software paradigms and silicon implementation, charting the course for industry-leading compute engines. You will own the exploration and formal definition of Instruction Set Architecture (ISA) extensions, drive microarchitectural innovations to counter dark silicon boundaries, and analyze next-generation workloads (including Generative AI, LLMs, graph analytics, and confidential computing). By pioneering novel hardware/software co-design methodologies, you will ensure our hardware is purpose-built to maximize execution efficiency for the computational demands of tomorrow. Key Responsibilities: · Long-Range Architecture Roadmap (N+1 & N+2): Drive the pathfinding and definition phases for microarchitectural features 3 to 5 years ahead of production. Define structural paradigms for the fetch/decode stages, execution pipelines, out-of-order schedulers, and multi-level memory hierarchies. · ISA Definition & Evolution: Evaluate, propose, and formally specify new Instruction Set Architecture capabilities (e.g., matrix vector extensions, custom compute instructions, dynamic scheduling helpers) to optimize future compute frameworks. · Emerging Workload & Performance Analysis: Profile, dissect, and project performance characteristics of next-generation workloads. Translate complex algorithmic bottlenecks into foundational microarchitectural requirements. · Hardware/Software Co-Design: Partner tightly with compiler teams, operating systems engineers, and application software architects to build end-to-end hardware acceleration capabilities, optimizing compilers alongside custom execution blocks. · Cycle-Accurate Modeling & Exploration: Oversee and guide the creation of C++/Python-based cycle-accurate simulation models to validate architectural concepts, trade-offs, performance speedups, and area/power efficiency (PPA). · Technical Leadership & Ecosystem Influence: Act as an elite technical individual contributor, influencing senior executive roadmaps and championing technical standards in international microarchitecture and ISA working committees. This job description is only an outline of the tasks, responsibilities and outcomes required of the role. The jobholder will carry out any other duties as may be reasonably required by his/her line manager. The job description and personal specification may be reviewed on an ongoing basis in accordance with the changing needs of Huawei Research and Development UK Limited. Required: · Deep Architecture Expertise: Proven track record in high-performance CPU core development (e.g., x86, ARM, or RISC-V). Deep expertise in Out-of-Order (OoO) execution, branch prediction, renaming, speculative execution, cache hierarchies, and coherency protocols. · ISA Mastery: Authoritative understanding of ISA-level designs, exception models, memory consistency models, and virtualization extensions. · Workload Profiling: Proficiency using hardware performance counters, simulation traces (SimPoints, execution traces), and profiling tools (VTune, Perf) on large-scale cloud, edge, or client workloads. · Advanced Modeling Skills: Strong hands-on experience developing cycle-accurate architectural simulators (such as gem5 or proprietary internal simulators) using C, C++, and Python. · Education & Experience: MS/PhD in Computer Engineering, Computer Science, or Electrical Engineering with a minimum of 12+ years of industry experience in CPU architecture and pathfinding. Desired: · Experience delivering multiple taped-out high-performance CPU silicon designs. · Active contributions to open-source architectural frameworks, compiler backends (LLVM/GCC), or open ISA working groups (e.g., RISC-V International). · Familiarity with advanced silicon packaging (chiplets, 3D stacking) and their microarchitectural implications.

Responsibilities

Lead the definition and modeling of next-generation high-performance CPU architectures and ISA extensions. Bridge the gap between software paradigms and silicon implementation to optimize execution efficiency for AI and cloud workloads.