Senior Principal Design Engineer at Cadence Design Systems

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

06 Jun, 26

Salary

0.0

Posted On

08 Mar, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Physical Layer Electrical Validation, SERDES, Test Chips, Hardware Architecture, Software Architecture, PCBs, FPGA Platforms, Labview, Python Automation, Test Plans, Oscilloscopes, Network Analyzer, BERT, Analog Design, PLL, Verilog RTL

Industry

Software Development

Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day Job Description JOB Role:Senior Principal Design Engineer: The responsibility entails leading pre silicon Physical Layer Electrical Validation infrastructure development as well as post silicon validation efforts primarily on Cadence's High Speed SERDES Test chips, ie, activities involving (but not limited to) designing the hardware and software architecture required to test the test chips (be it the test PCBs, controlling FPGA platforms, Labview/python automation for controlling the HW etc), defining test plans for rigorously testing the compliance of the Test chips to the Physical Layer Electrical specifications, implementing these tests as planned, generating high quality test reports based on the test results etc. What we are looking for in potential candidates is listed below. Minimum Qualifications: • 10-15 years (with Btech) or 8-13 years (with Mtech) of experience in Post-Silicon Physical Layer Electrical Validation • Deep Physical Layer electrical validation experience on AT LEAST ONE High speed SERDES protocol like PCIe, USB, DP, ethernet, SRIO, JESD204, DDRIO etc • Strong hands on Experience in using lab equipment such as Oscilloscopes, Network Analyzer, Bit Error Rate Tester (BERT) etc Preferred Qualifications: • Experience managing small teams (at least 2 members and above) is a strong plus • Experience leading the complete post silicon validation efforts for at least one full project • 1-2 years of experience in Analog, PLL,FPGA Design, PCB schematic and layout design & Prototyping is a strong plus • Pre-Silicon IP/SoC Physical Layer Electrical Validation experience related to board bring-up & Debug. • Familiarity with Verilog RTL coding, FPGA coding, Labview, python, C/C++, TCL • Experience conducting hiring interviews and mentoring new hires • Candidates are expected to be passionate about analog and digital electronic circuit design aspects as well as signal processing related aspects. We’re doing work that matters. Help us solve what others can’t. Additional Jobs Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization. Read the policy(opens in a new tab) We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact staffing@cadence.com. Privacy Policy: Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab). E-Verify Cadence participates in the E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

Responsibilities

The role involves leading pre-silicon Physical Layer Electrical Validation infrastructure development and post-silicon validation efforts on High Speed SERDES Test chips, including designing necessary hardware/software architecture and defining rigorous test plans. Responsibilities also cover implementing these tests, generating high-quality test reports based on results, and managing activities related to test PCBs, FPGA platforms, and automation using tools like Labview/Python.