Senior Principal IP Design Engineer at GLOBALFOUNDRIES U S 2 LLC

Bangalore, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

22 May, 26

Salary

0.0

Posted On

21 Feb, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

RTL Development, Microarchitecture, CPU Core Design, Performance Optimization, Power Efficiency, Area Optimization, Functional Verification, Timing Analysis, System Verilog, Verilog, VHDL, Branch Prediction, Out-of-Order Execution, Vector Instructions, Cache Subsystems, RISC-V

Industry

Semiconductor Manufacturing

Description

Senior Principal IP Design and Microarchitecture Engineer for AI CPU Micro architect We are seeking an experienced CPU Micro architect. Responsible for Defining, leading and owning RTL development of a performance efficient, low-power CPU core. The candidate will be responsible for all aspects of the design including Functional Features, Performance, Power, and Area. You will: Drive the micro-architecture and design of a critical CPU block or multiple blocks of a CPU core Explore high-performance strategies working with the CPU modeling team Perform Microarchitecture development and specification- from early high-level architectural exploration, through microarchitectural research and arrive at detailed specifications Configure Design Features Development, assessment, and refinement of RTL design to target power, performance, area, and timing goals Perform Functional verification support and assist in the design verification strategy Assist with the verification of RTL design performance goals Partner with a multi-functional engineering team to implement and validate physical design aspects of timing, area, reliability, testability, and power Ideally, you’ll have: Hands-on working knowledge of the pipeline stages of an in-order or out-of-order high-performance CPU core Thorough knowledge of microprocessor architecture including expertise in one or more of the following areas: Instruction fetch and decode, branch prediction techniques Instruction scheduling, register renaming, Reorder Buffer (ROB) Out-of-order execution Integer and Floating-point execution Scalar and Vector instructions Load/Store execution Instruction and Data Prefetch Cache and memory subsystems Knowledge of Cache coherency and memory consistency Knowledge of System Verilog, Verilog and/or VHDL Experience with simulators and waveform debugging tools. Knowledge of logic design principles along with timing and power implications Master’s with 8-11 years of experience, PhD + 5-7 years of work experience A plus if you have: Experience with designing RISC-V, ARM, and/or MIPS CPU Experience with Hardware multi-threading, virtualization, and SIMD designs Experience with real-time microcontroller designs Understanding of high-performance techniques and trade-offs in a CPU microarchitecture Understanding of low-power microarchitecture techniques Experience using a scripting language such as Perl or Python Understanding of CPU integration at SoC level Understanding of Safety and Security microarchitecture and proven technologies, MIPS can accelerate development and deployment of RISC-V based solutions. Information about our benefits you can find here: https://gf.com/about-us/careers/opportunities-asia We shape what's essential At GlobalFoundries you will find a vibrant work environment where collaboration and innovation thrive. Our diverse and global team shares a culture of respect and inclusivity, representing the best in the industry. We celebrate success together and are united by our dedication to excellence and our desire to improve and empower the world.

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Responsibilities

The role involves defining, leading, and owning the RTL development for a performance-efficient, low-power CPU core, covering functional features, performance, power, and area aspects. Responsibilities include driving micro-architecture design for critical CPU blocks and exploring high-performance strategies in collaboration with the modeling team.