Senior Principal Physical Design Engineer at MaxLinear, Inc.

, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

18 Sep, 26

Salary

0.0

Posted On

20 Jun, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

ASIC Physical Design, PPA Optimization, Full-chip PD Closure, Signoff Readiness, EDA Vendor Management, Flow and Methodology Definition, Mentoring, Tape-out Execution, Chip Architecture, Collaboration, Technical Leadership, Implementation Strategy

Industry

Semiconductor Manufacturing

Description

Responsibilities MaxLinear is seeking a Senior Principal Physical Design Engineer with Minimum 12 years of ASIC physical design experience, excellent collaboration and teamwork capabilities, responsible to hire talent and mentor. Ability to define and drive flows and methodologies, resolve design and flow issues, work with front-end teams, and maintain EDA vendor relationships. Multiple successful tape out, strong communication, and ability to handle a dynamic environment. Define execution strategy for large programs, own full-chip PD or major subsystems, ensure PPA targets and tapeout readiness, drive alignment across teams, new technology adoption, and organization-wide improvements. Ownership of chip-level PD closure, signoff readiness, and delivering silicon for a wide range of applications. Define execution strategy for large programs Own full-chip PD or major subsystems. Define implementation strategy and ensures PPA targets and tapeout readiness. Represent the team in program-level forums. Drive alignment across ASIC, EDA, layout, and program teams. Drive new technology adoption, flow definition, and organization-wide improvements. Ownership of Chip-level PD closure plan, signoff readiness reviews, escalation playbooks, tool/flow adoption plan, org-wide training artifacts. Will be responsible for delivering silicon for a wide range of applications Qualifications Minimum 12 years of ASIC physical design experience Should have excellent collaboration and teamwork capabilities across various chip development disciplines. Will be responsible to hire talent and mentor, build expertise, and grow each team member Ability to define and drive flows and methodologies to optimize physical design work, define guidelines and checklists, drive execution, and track progress Ability to resolve design and flow issues related to physical design through the identification of potential solutions and drive resolution Experience in working with the front-end teams to understand chip architecture and drive physical aspects early in the definition cycle Experience working relationships with EDA Vendors Multiple successful tape out Excellent communication (oral and written) skills Ability to present to and interface with internal customers Ability to handle a dynamic environment and to coordinate team action Masters’ / Bachelor’s Degree in Electronics/Electrical Engineering Company Overview MaxLinear is a global, NASDAQ-traded company (MXL) where the entrepreneurial spirit is alive and well. We are a fabless system-on-chip product company, striving to improve the world’s communication networks for everyone through our highly integrated radio-frequency (RF), analog, digital, and mixed-signal semiconductor solutions for access and connectivity, wired and wireless infrastructure, and industrial and multi-market applications. We hire the best people in the industry and engage them in some of the most exciting opportunities that connect the world we live in today. Our growth has come from innovative, bold approaches to solving some of the world’s most challenging communication technology problems in the most efficient and effective manner. MaxLinear began by developing the world’s first high-performance TV tuner chip using standard CMOS process technology. Others said we couldn’t achieve the extremely high-performance requirements using CMOS, but we proved them wrong and achieved enduring global market leadership with our designs. Since then, we’ve developed a full line of products that drive 4G and 5G infrastructure; enable data center, metro and long-haul optical interconnects; bring 10Gbit to the home; power the IoT revolution; and enable robust and reliable communication in harsh industrial environments. Over the years, we’ve expanded through organic growth and through several acquisitions that have perfectly complemented our existing portfolio and enabled us to deliver complete end-to-end solutions in our target markets. One such example was the acquisition of Intel’s Home Gateway Platform Division that added Wi-Fi, Ethernet, and Broadband Gateway Processor SoC technology to our connected home portfolio creating a complete and scalable platform of connectivity and access solutions to fully address our customers’ needs. Our headquarters are in Carlsbad, near San Diego, California. We also have major design centers in Irvine and San Jose, California; Valencia, Spain; Bangalore, India; Munich, Germany; Israel; and Singapore. We have approximately 1,200 employees, a substantial majority of whom have engineering degrees and include masters and Ph.D. graduates from many of the premiere universities around the world. Our employees thrive on innovation, outstanding execution, outside-the-box thinking, nimbleness, and collaboration. Together, we form a high-energy business team that is focused on building the best and most innovative products on the market.

Responsibilities

Lead full-chip physical design closure and define execution strategies for large ASIC programs to ensure PPA targets and tapeout readiness. Responsible for driving alignment across cross-functional teams, adopting new technologies, and mentoring talent.