Y-Axis Jobs Logo
Send us feedback
telephone  +91 7670 800 001
Log in Sign up Try Premium
Senior Principal Verification Engineer at onsemi
Bangalore, karnataka, India -
Full Time

Start Date

Immediate

Expiry Date

16 Sep, 26

Salary

0.0

Posted On

18 Jun, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

No

Skills

SystemVerilog, UVM, OVM, ASIC Verification, SoC Verification, Python, Perl, Tcl, C/C++, Gate-Level Simulation, Power-Aware Verification, Formal Verification, AXI/AHB/APB, I2C, SPI, UART

Industry

Semiconductor Manufacturing

Description
We are seeking an experienced Senior Principal ASIC/SoC Verification Engineer to join our dynamic and fast‑paced engineering team. In this role, you will be responsible for ensuring the functional correctness, robustness, and overall quality of our cutting‑edge semiconductor and SoC designs. If you thrive in a collaborative environment and enjoy solving complex technical challenges, this opportunity is an excellent fit. #LI-RG1 onsemi (Nasdaq: ON) is driving disruptive innovations to help build a better future. With a focus on automotive and industrial end-markets, the company is accelerating change in megatrends such as vehicle electrification and safety, sustainable energy grids, industrial automation, and 5G and cloud infrastructure. With a highly differentiated and innovative product portfolio, onsemi creates intelligent power and sensing technologies that solve the world’s most complex challenges and leads the way in creating a safer, cleaner, and smarter world. More details about our company benefits can be found here: https://www.onsemi.com/careers/career-benefits [https://www.onsemi.com/careers/career-benefits] We are committed to sourcing, attracting, and hiring high-performance innovators, while providing all candidates a positive recruitment experience that builds our brand as a great place to work.
Responsibilities
Develop and execute comprehensive SoC/IP-level verification plans to ensure functional correctness and robustness of semiconductor designs. Architect UVM-based testbenches and perform advanced verification including gate-level and power-aware simulations.