CANDIDATE VALUE PROPOSITION

✔ Work across multiple high-visibility hardware projects (Diamond Lake, Miraf, Maya, etc.).
✔ Collaborate with diverse teams and act as a trusted expert in synthesis and flows.
✔ Hybrid flexibility with expected 3 days onsite in Mountain View.
✔ Long-term contract stability (18+ months).

REQUIRED QUALIFICATIONS

• 7+ years experience in RTL synthesis & physical implementation using Synopsys tools (Fusion Compiler, Design Compiler, PrimeTime).
• Strong expertise with RTLA & PrimePower RTL flows, including switching activity modeling and scenario analysis.
• Proficiency in TCL/Python scripting for flow automation and debugging.
• Solid knowledge of timing constraints, UPF, and low-power methodologies.
• Linux and bash scripting experience.
• Familiarity with advanced process nodes (timing, congestion, power closure).

PREFERRED QUALIFICATIONS

• Experience collaborating with EDA vendors on tool evaluation & profiling.
• Exposure to automation/reporting dashboards for synthesis metrics.
• Contributions to flow migration or tool benchmarking initiatives.

TOP 3 HARD SKILLS (MUST-HAVE)

• Synthesis expertise – 7+ years
• Fusion Compiler expertise – 7+ years
• PrimePower / RTL flows expertise – 7+ years
  Job Type: Contract
  Pay: $80.00 - $95.00 per hour

Experience:

• Synthesis expertise: 7 years (Required)
• Fusion Compiler: 7 years (Required)
• PrimePower / RTL flows: 7 years (Required)

Ability to Commute:

• Mountain View, CA 94035 (Preferred)

Work Location: In perso

ROLE OVERVIEW

We are seeking a Senior Implementation Engineer with deep expertise in RTL-to-GDSII flows using Synopsys Fusion Compiler and RTL Architect (RTLA). You will play a pivotal role in driving synthesis quality, PPA optimization, and methodology development for advanced node SoC designs. This role provides the opportunity to collaborate across multiple high-impact hardware projects while acting as a tool and flow expert.

WHAT YOU’LL DO

• Own and optimize RTL-to-GDSII flows (synthesis, placement, routing, and signoff) using Synopsys Fusion Compiler.
• Develop and maintain RTLA-based power estimation & optimization flows, integrating with PrimePower RTL.
• Collaborate with RTL & PD teams to define timing constraints, UPF-based power intent, and switching activity annotations for accurate power analysis.
• Drive methodology improvements for RTL power estimation, scenario-based analysis, and dynamic power optimization.
• Debug & converge synthesis flows (constraint validation, floorplan integration, flow automation).
• Interface with EDA vendors (Synopsys preferred) for tool evaluation, issue reporting, and roadmap discussions.
• Provide training & documentation on best practices for synthesis and low-power design.