Senior SerDes Verification Engineer at Advanced Micro Devices, Inc

Bangalore, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

04 Sep, 26

Salary

0.0

Posted On

06 Jun, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

UVM, SystemVerilog, VHDL, SerDes Architecture, PCIe, UCIe, Ethernet, USB, DDR Protocol, Signal Integrity Analysis, Python, Perl, Functional Coverage, Assertions, Debugging, Simulation

Industry

Semiconductor Manufacturing

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. As a SerDes Verification Architect, you will be responsible for the verification and validation of high-speed SerDes interfaces, including testing data integrity, performance, and protocol compliance. You will work closely with hardware and design teams to ensure that SerDes designs meet the required specifications, operating parameters, and quality standards. Key Responsibilities: Verification of SerDes Designs: Develop and execute verification plans and testbenches for SerDes IPs (Intellectual Property) and subsystems to ensure they meet functional and performance requirements. Testbench Development: Design and implement verification testbenches using industry-standard verification methodologies (e.g., UVM, SystemVerilog, VHDL). Simulation and Debugging: Perform simulations, analyze results, and debug issues related to timing, protocol errors, and other design anomalies in SerDes blocks. Performance Evaluation: Evaluate and validate performance characteristics of SerDes systems including jitter, bit error rates (BER), signal integrity, eye diagrams, and other key metrics. Protocol Compliance Testing: Verify adherence to relevant SerDes protocols such as UCIe, PCIe, Ethernet, USB, DDR, DisplayPort, or custom protocols. Automated Testing: Develop automated regression tests to ensure the robustness and stability of the SerDes design over multiple versions and iterations. Collaboration: Work closely with the design, hardware, and software teams to troubleshoot issues, implement fixes, and verify design changes. Documentation: Create detailed reports and documentation on verification results, test scenarios, and issues found during testing. Verification methodology: Provide feedback for design and verification process improvements and contribute to innovation in verification strategies and methodologies. Experience: Experience in SerDes verification or high-speed communication verification. Strong hands-on experience with verification methodologies such as UVM, SystemVerilog, or other simulation-based verification tools. Knowledge of high-speed serial protocols such as UCIe, PCIe, Ethernet, USB, DDR, or custom protocols. Experience in analyzing and interpreting signal integrity issues, jitter, BER, and eye diagrams. Skills: Solid understanding of SerDes architectures, link training, and equalization. Strong debugging skills, with the ability to work across multiple domains (timing, protocol, performance). Familiarity with hardware description languages (HDL) like VHDL or Verilog. Strong analytical, problem-solving, and communication skills. Experience with DDR protocol (e.g., DDR3, DDR4, DDR5) for memory interface verification. Understanding of UCIe protocol and its role in chiplet-to-chiplet communication. Preferred Skills: Experience with Python, Perl, or similar scripting languages for automation. Exposure to high-speed memory interface design and verification, including DDR controller IP verification. Functional coverage, assertions knowledge in SV/UVM. Ability to work in a fast-paced environment and manage multiple verification tasks. Strong team player with good interpersonal and communication skills. #LI-PK2 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Responsibilities

The role involves developing and executing verification plans and testbenches for high-speed SerDes IPs to ensure functional and performance compliance. Key duties include performing simulations, debugging timing and protocol errors, and validating metrics like jitter and bit error rates.