Senior Signal Integrity Engineer (NetSec) at Palo Alto Networks

Santa Clara, California, United States -

Full Time

Start Date

Immediate

Expiry Date

05 Jan, 26

Salary

224500.0

Posted On

07 Oct, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Signal Integrity, High-Speed PCB Design, ASIC Package Design, Power Integrity Analysis, EM Simulation, PCB Fabrication Process, Troubleshooting, Failure Analysis, Lab Measurements, Channel Analysis, Serdes Interfaces, Design Validation, Mentoring, Collaboration, Innovation, Communication

Industry

Computer and Network Security

Description

Company Description Our Mission At Palo Alto Networks® everything starts and ends with our mission: Being the cybersecurity partner of choice, protecting our digital way of life. Our vision is a world where each day is safer and more secure than the one before. We are a company built on the foundation of challenging and disrupting the way things are done, and we’re looking for innovators who are as committed to shaping the future of cybersecurity as we are. Who We Are We take our mission of protecting the digital way of life seriously. We are relentless in protecting our customers and we believe that the unique ideas of every member of our team contributes to our collective success. Our values were crowdsourced by employees and are brought to life through each of us everyday - from disruptive innovation and collaboration, to execution. From showing up for each other with integrity to creating an environment where we all feel included. As a member of our team, you will be shaping the future of cybersecurity. We work fast, value ongoing learning, and we respect each employee as a unique individual. Knowing we all have different needs, our development and personal wellbeing programs are designed to give you choice in how you are supported. This includes our FLEXBenefits wellbeing spending account with over 1,000 eligible items selected by employees, our mental and financial health resources, and our personalized learning opportunities - just to name a few! At Palo Alto Networks, we believe in the power of collaboration and value in-person interactions. This is why our employees generally work full time from our office with flexibility offered where needed. This setup fosters casual conversations, problem-solving, and trusted relationships. Our goal is to create an environment where we all win with precision. Job Description Your Career As a contributor in the Network Security Platform Hardware development team, you will play a key role in the complete design cycle of Palo Alto Networks Firewall and SD-WAN hardware including: selecting components; modeling and simulating memory and serdes interfaces; modeling PDN networks; defining PCB routing constraints; reviewing PCB layout; developing test plans; performing hands-on measurements to validate critical interfaces. Within the Hardware team, you collaborate closely with Board Design, ASIC Design, PCB Layout, and Validation Test. You will also collaborate cross-functionally with Product Management, Platform Software, and Operations Supply Base Management & Component Engineers. Your Impact Collaborate with a cross-functional team including: ASIC, Board design, PCB layout, Operations supply base management, Platform Software Evaluate design tradeoffs and optimize design performance / risk / cost / manufacturability Contribute to ASIC package design for SI Model complex 3-dimensional structures in field simulation software Simulate Channel Analysis for high speed serdes and memory interfaces Design and analyze high-speed serial links (56G and beyond) and their compliance to internal specs and standards Create and verify module/package and PCB layout rules: perform pre- and post-route signal integrity analysis of ASIC and multi-chip-module designs Model and analyze power delivery networks for ASIC/package/module and PCB Create SI test plan for coverage of all serdes, memory, and external IO interfaces Drive creation and implementation for required test infrastructure (tools, scripts, etc.) with external vendors and internal software teams Perform lab measurements for design validation and simulation correlations Drive methodology enhancements and automation - improving performance and efficiency Mentor junior engineers and interns Qualifications Your Experience Strong background in hands-on design and validation of high-speed PCB and ASIC package development Power integrity design and analysis and well versed in PI simulation tool such as PowerSI/DC, etc. Working experience with high speed NRZ and PAM4 Serdes Self-motivated with demonstrated teamwork and communication skills; ability to drive outcomes with both vendors and internal teams Out of the box thinking with the strong desire to innovate are essential Strong EM knowledge and in-depth expertise of EM simulation tools such as HFSS/PowerDC-SI/ADS/SiSoft Familiar with PCB fabrication process, dielectric material and stackup design Solid knowledge of the IEEE 802.3/ OIF specifications and COM simulations Strong lab skills and measurement experience are required (VNA, TDR, Real Time Scope, Sampling scope, BERT) Demonstrated ability in troubleshooting and failure analysis Ability to contribute on multiple projects and work in a dynamic, collaborative environment Knowledge of optical transceivers highly desired Additional Information The Team To stay ahead of the curve, it’s critical to know where the curve is, and how to anticipate the changes we’re facing. For the fastest growing cybersecurity company, the curve is the evolution of cyberattacks, and the products and services that proactively address them. Our engineering team is at the core of our products – connected directly to the mission of preventing cyberattacks. They are constantly innovating – challenging the way we, and the industry, think about cybersecurity. These engineers aren’t shy about creating products to solve problems no one has tackled before. They define the industry, instead of waiting for directions. We need individuals who feel comfortable in ambiguity, excited by the prospect of challenge, and empowered by the unknown risks facing our everyday lives that are only enabled by a secure digital environment. Our engineering team is provided with an unrivaled opportunity to build the products and practices that will support our company growth over the next decade, defining the cybersecurity industry as we know it. If you see the potential of how incredible people & products can transform a business, this is the team for you. If you don’t wait for directions, instead, identifying new features and opportunities we have to just get better, this is your new career. Why Palo Alto Networks? Develop NPI hardware in a creative and innovative environment Imagine new opportunities in areas that matter and will impact the world you live in Be a part of a high performing team of the world's best cybersecurity companies FLEXwork arrangements to support you in working in the way that you work best Compensation Disclosure The compensation offered for this position will depend on qualifications, experience, and work location. For candidates who receive an offer at the posted level, the starting base salary (for non-sales roles) or base salary + commission target (for sales/commissioned roles) is expected to be between $139000/YR - $224500/YR. The offered compensation may also include restricted stock units and a bonus. A description of our employee benefits may be found here. Our Commitment We’re problem solvers that take risks and challenge cybersecurity’s status quo. It’s simple: we can’t accomplish our mission without diverse teams innovating, together. We are committed to providing reasonable accommodations for all qualified individuals with a disability. If you require assistance or accommodation due to a disability or special need, please contact us at [email protected]. Palo Alto Networks is an equal opportunity employer. We celebrate diversity in our workplace, and all qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or other legally protected characteristics. All your information will be kept confidential according to EEO guidelines.

Responsibilities

You will play a key role in the design cycle of Palo Alto Networks Firewall and SD-WAN hardware, including selecting components and modeling interfaces. Collaborate closely with various teams to evaluate design tradeoffs and optimize performance.