Senior Silicon Design Engineer at Advanced Micro Devices, Inc

George Town, Penang, Malaysia -

Full Time

Start Date

Immediate

Expiry Date

01 Jul, 26

Salary

0.0

Posted On

02 Apr, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

ASIC Design Verification, Testbench Architecture, UVM, SystemVerilog, Verilog, PCIe, High Speed IO Protocol, Serdes PHY, Low Power Verification, Formal Verification, Communication Skills

Industry

Semiconductor Manufacturing

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: PCIe SubSystem team delivers industry leading high-performance interconnects IP for all AMD products including dGPU, APU, Server and Game consoles. PCIe IP is one of the most important IP in all AMD’s projects. So, this role provides a great opportunity to work on the most advanced PCIe technology with the global team Architects/Designers/DV on PCIe SS IP Verification. THE PERSON: People who have the passion to work on leading edge technology, who have good communication skills will be preferred in this role. KEY RESPONSIBILITIES: Develop and update infrastructure and environment for IP level design verification. Closely working with Design and Architecture team to develop new verification component Responsible for PCIe SS IP new features verification plan and verification closure PREFERRED EXPERIENCE: Solid background with ASIC design verification flow and multiple ASIC tape out experience with 8+ years Team leading experience and experienced on testbench architecture. Solid knowledge on UVM, SystemVerilog , Verilog is a must Solid background on PCIe is preferred, other high speed IO protocol or Serdes PHY is also a big plus Low power verification work experience is a plus. Knowledge on formal verification is a plus. Fluent written English for technical discussion among global team, vocal is a plus ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering with 5+ years’ experience in digital ASIC/SOC design verification. LOCATION: Penang, Malaysia #LI-JL1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Responsibilities

Develop and update infrastructure and environment for IP level design verification. Work closely with the Design and Architecture team to develop new verification components and manage verification plans.