Senior Silicon Design Verification Engineer at Advanced Micro Devices, Inc

George Town, Penang, Malaysia -

Full Time

Start Date

Immediate

Expiry Date

06 May, 26

Salary

0.0

Posted On

05 Feb, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Silicon Design, Verification, Digital Design, Processor Architecture, Communication Skills, Analytical Skills, Problem-Solving, ASIC Verification, Debugging, UVM, Verilog, System Verilog, C, C++, Scripting Languages, SystemC, TLM

Industry

Semiconductor Manufacturing

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As a member of the Central Engineering Group, you will help bring to life cutting-edge designs. The focus of this role is to plan, build, and execute the verification of new and existing features for High Speed IO Protocol IPs (USB, PCIe, Ethernet, UFS) that is used in AMD’s product portfolio resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBLITIES: Able to work well inside team/cross functional team Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified. Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases. Estimate the time required to write the new feature tests and any required changes to the test environment. Build the directed and random verification tests. Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues . Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements. PREFERRED EXPERIENCE: Experience in IP level ASIC verification Experience in debugging firmware and RTL code using simulation tools. Experience in using UVM testbenches and working in Linux and Windows environments. Good understanding with UVM, Verilog, System Verilog, C, and C++ USB,UFS,Ethernet,PCIE,AXI knowledge is a plus Good understanding and hands-on experience in the UVM concepts and SystemVerilog language. (SVA, UVM scoreboard) Good working knowledge of SystemC and TLM with some related experience. Scripting language experience: Perl, Ruby, Makefile, shell preferred. Over 5 yrs of digital IP verification with SV/UVM/formal verification or new methodology of the industry ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering . LOCATION: Penang, Malaysia #LI-JL1 #LI-Hybrid DV Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Responsibilities

The role involves planning, building, and executing the verification of new and existing features for High Speed IO Protocol IPs. The engineer will collaborate with various teams to ensure no bugs are present in the final design.