Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Mountain View, CA, USA; San Diego, CA, USA.

MINIMUM QUALIFICATIONS:

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 5 years of experience with computer architecture concepts, including microarchitecture, cache hierarchy, pipelining, and memory subsystems.
• 5 years of experience in SoC power management or low power design/methodology.
• Experience with Application-Specific Integrated Circuit (ASIC) low power flows and power management concepts.

PREFERRED QUALIFICATIONS:

• Master’s Degree or PhD in Electronics or Computer Engineering/Science, with an emphasis on computer architecture, performance and power analysis.
• 8 years of experience in SoC power management or low power design/methodology.
• Experience in CPU power in mobile SoCs from CPU architecture and design to schedulers, governors and post-silicon tuning for power and performance.
• Experience with ASIC power modeling/estimation, defining power goals, power roll-ups, power/voltage domains design and low power architectures/optimization techniques.
• Experience with software and architectural design decisions on system power and thermal behavior.
• Experience with ASIC design flows from concept to post-silicon.

• Define and drive low power solutions for Google System on a Chips (SoC) to optimize Power-Performance-Area (PPA) under peak current and thermal constraints with a focus on the CPU subsystem.
• Define power key performance indicators and SoC/IP-level power goals, guide architecture, design and implementation to achieve power goals, create power models, perform power roll ups and track power throughout the design cycle.
• Propose and drive power optimizations, both hardware and software, throughout the design process from concept to mass productization.
• Drive power-performance trade-off analysis for engineering reviews and product road-map decisions.
• Perform post-silicon characterization and productization of power features.
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