Senior Soft IP Design Engineer at LATTICE SEMICONDUCTOR CORPORATION

George Town, Penang, Malaysia -

Full Time

Start Date

Immediate

Expiry Date

24 Jul, 26

Salary

0.0

Posted On

25 Apr, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

FPGA IP Design, RTL Design, High-speed SERDES, PCIe, Ethernet, CPRI, JESD204B/C, DDR4, LPDDR4, Logic Verification, Timing Closure, C/C++, Perl, TCL, Python, Hardware Validation

Industry

Semiconductor Manufacturing

Description

Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for. Responsibilities & Skills Responsibilities: The Employee should be a passionate individual with technical leadership capabilities to build Connectivity IP portfolios for Lattice FPGA. The Employee should have the ability to work closely with architect to translate specifications into high-speed RTL design, for the best Performance, Power and logic utilization. Qualifications: BS/MS/PhD in Electronics or Computer Engineering minimum of 5 years of FPGA IP design experience. Independent and self-motivated, capable of executing under dynamic environment and uncertainties. Experience in high speed SERDES protocols (e.g.: PCIe, Ethernet, CPRI or JESD204B/C) or Memory (DDR4, LPDDR4, etc) is a plus. Hands-on experience in FPGA RTL design, logic verification, debug and timing closure is preferred. Programming skills (e.g.: C/C++, Perl, TCL or Python). Experience in hardware validation or hardware interoperability test is a plus. Experience in soft IP packaging, example design and testbench development will be an added advantage.

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Responsibilities

The employee will provide technical leadership to build Connectivity IP portfolios for Lattice FPGA. They will work closely with architects to translate specifications into high-speed RTL designs optimized for performance, power, and logic utilization.