Senior STA Engineer, Sub-chip at NVIDIA

Yokneam Ilit, Haifa District, Israel -

Full Time

Start Date

Immediate

Expiry Date

23 Jun, 26

Salary

0.0

Posted On

25 Mar, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Static Timing Analysis, STA, Physical Design, HSIO, Chiplet, FC Level, Prime Time, Timing Paths, SDC Generation, Timing Ecos, RTL, DFT, Signoff, AI Optimization, Data Analysis, TCL

Industry

Computer Hardware Manufacturing

Description

NVIDIA is looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company. What you'll be doing: Perform advanced Static Timing Analysis (STA) for HSIO at chiplet and FC level. Running Prime Time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation. Identify convergence risks and work closely with physical design, RTL and DFT teams, ensuring convergence throughout various project stages. Responsible for a full timing closer and quality approval from pre-layout STA model through signoff. AI use for timing optimization and data analysis. What we need to see: B.SC./ M.SC. in Electrical Engineering. At least 5+ years of hands-on STA experience. Experience in Prime Time and signoff methodologies. A great teammate who thrives in a collaborative environment. AI tools orientation or alternatively a desire to learn. Ways to stand out from the crowd: Agentic Frameworks. AI prompting experience. Experience in Linux environments. TCL, Python, shell scripting abilities. Experience with data collection and analysis. NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry! NVIDIA is the world leader in accelerated computing. NVIDIA pioneered accelerated computing to tackle challenges no one else can solve. Our work in AI and digital twins is transforming the world's largest industries and profoundly impacting society. Learn more about NVIDIA.

Responsibilities

The engineer will perform advanced Static Timing Analysis (STA) for HSIO at chiplet and FC levels, running Prime Time, debugging paths, and generating SDC constraints. Responsibilities include ensuring timing convergence throughout project stages, from pre-layout STA model through signoff, and utilizing AI for timing optimization.