What you’ll be doing

You’ll work across the full front-end design flow, including:

Developing synthesizable SystemVerilog / Verilog RTL

Translating architecture and ISA requirements into microarchitecture

Designing processor, accelerator and complex SoC blocks

Integrating internal and third-party IP

Working closely with verification, architecture and physical design teams

Supporting synthesis, timing closure and PPA optimisation

Driving CDC / RDC quality and sign-off

Implementing low-power techniques including clock gating, power gating and memory power management

Supporting gate-level simulation, FPGA and emulation activity

Taking real ownership of design blocks through to tape-out

What they’re looking for

You’ll ideally have:

5+ years of ASIC / SoC RTL Design experience

Strong SystemVerilog or Verilog

Experience with processors, accelerators or complex SoCs

Strong microarchitecture experience

Experience with synthesis and timing-aware RTL design

• Good knowledge of AMBA / AXI / AHB / APB