YOU ARE:

We are seeking a highly motivated and innovative Sr Staff digital design engineer with extensive knowledge of ASIC development flow. The ideal candidate is passionate about technology, driven by challenges, and eager to work on cutting-edge SerDes products. You have a solid theoretical and practical background in high-speed serializer and data recovery circuits, and you thrive in a fast-paced, dynamic environment. You bring a wealth of experience in digital design and verification, and you are proficient in Verilog. You are a proactive problem-solver, capable of working independently and as part of a team, with the ability to guide junior peers and network with senior internal and external personnel. Your excellent communication skills enable you to interact effectively with different design groups and customer support teams. You are self-motivated, proactive, and committed to producing high-quality designs while meeting tight deadlines.

• Developing and verifying ASIC RTL designs at both chip and block levels.
• Writing block-level test cases, including constrained directed random tests.
• Implementing digital design methodologies, DFT insertion, and synthesis constraints and flows.
• Enhancing and maintaining existing SERDES PHY IPs for multiple protocols.
• Collaborating with Application Engineers to resolve technical issues and provide customer support.
• Guiding junior peers and networking with senior personnel within and outside the functional area.