Do you want to contribute to the backbone of some of the world’s most popular System-on-Chips (SoCs)? Are you technically savvy with a passion for learning and teaching?
As a Senior Design Verification Engineer at Arteris, you will work with an expert team to design and deliver interconnect & memory hierarchy solutions for some of the world’s most sophisticated mobile, telecom, automotive, and consumer SoC designs.
You will create designs in a powerful language that blends traditional RTL with leading-edge software to provide extremely configurable, testable, and high-quality solutions. You will go home at the end of the day amazed at all the places where your creations end up.
You will have the opportunity to be part of a proven-successful startup, and to influence development environment, architecture, verification, and everything in-between – you will no longer be stuck in a silo or just a cog in the machine. Your co-workers will be an experienced team of industry experts that love what they do.

EXPERIENCE REQUIREMENTS / QUALIFICATIONS:

• 10 or more years of design and verification experience and a plus in interconnect verification experience
• Verification flow enhancements using a scripting language such as Shell scripts, Python & JavaScript
• Strong RTL (Verilog) and UVM/C test bench debugging skills
• Experience integrating vendor provided VIPs for unit and system level verification
• Experience with Arm AMBA protocols
• This opportunity involves high performance, low power designs on a highly visible project

EDUCATION REQUIREMENTS:

• MS degree in EE, CS, or equivalent preferred. BS degree minimum.

• Advanced UVM based test bench development and debugging
• Defining, documenting, developing, and executing RTL verification test/coverage at system level
• Performance verification and power-aware verification
• Triaging Regressions, Debugging RTL designs in Verilog and System Verilog
• Help improve and refine verification process, methodology, and metrics
• UVM expertise on complex SoC projects from test bench development to verification closure