Senior Staff Engineer Design at Infineon Technologies AG Australia

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

12 Feb, 26

Salary

0.0

Posted On

14 Nov, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Physical Design, Synthesis, Floor Planning, Place and Route, Clock Tree Synthesis, IP Integration, Extraction, Physical Verification, Automation, RTL Analysis, STA, EM/IR, Version Management, Communication Skills, QA Test Plans, Verification Methodology

Industry

Semiconductor Manufacturing

Description

Responsible for planning and execution of all aspects of Physical Design including Synthesis, Floor planning, Place and Route, Clock Tree Synthesis, IP integration, Extraction, Physical Verification, and taking blocks to the closure. Responsible for planning and execution of all aspects of Physical Design including Synthesis, Floor planning, Place and Route, Clock Tree Synthesis, IP integration, Extraction, Physical Verification, and taking blocks to the closure. Design Application Engineering (DAE) will be responsible for supporting project teams using Infineon Design System (Flows, Design Package & Design assistance). Responsible for automation of manual processes (including design flow/design package qualification mechanisms, generation of test reports/dashboards etc.) and providing automation requirements for reducing manual steps in qualification. The candidate should have a minimum of 6 years of relevant working experience in Physical Design implementation areas including Synthesis, LEC, and PnR as well as good exposure to signoff areas, particularly power, timing, and IR signoff. One should have a deep understanding of and be able to be cater to design concerns across semi-custom design flows, including RTL analysis, synthesis, LEC, Place and Route, STA, EM/IR, and physical verification. One should be able to identify flow gaps and provide automation on need base to perform all design activities in the most efficient and correct-by-construction way. One should be able to evaluate solutions from multiple available options and be able to perform trade-offs between technical features. Analyse the results and any inconsistency issues to be reports via bug tracking system. One will work with R&D in Infineon globally and EDA tool vendors to resolve issues across semi-custom design flows. One will coordinate with IT and EDA tool license teams to provide an infrastructure aligned with project needs. One should have exposure to basic version management using any of Clearcase/Perforce/Cliosoft/Git. You should possess excellent communication skills to interact effectively with peers and customers in a clear and honest manner with consistent and open to learning new technical areas if the need arises. You should define and monitor key test metrics, build regression status reporting dashboard, Develop and execute QA test plans, verification methodology & test strategies for digital block/chip level to maximize the coverage of features/methodology supported in the technologies/Design Flows. We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills.

How To Apply:

Incase you would like to apply to this job directly from the source, please click here

Responsibilities

Responsible for planning and execution of all aspects of Physical Design including Synthesis, Floor planning, Place and Route, and Physical Verification. The role also involves supporting project teams and automating manual processes to enhance efficiency.