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Senior Staff Engineer Design at Infineon Technologies AG Australia
Bengaluru, karnataka, India -
Full Time

Start Date

Immediate

Expiry Date

12 Feb, 26

Salary

0.0

Posted On

15 Nov, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

No

Skills

DFT Implementation, Verification, Post Silicon Debug, SOC Level Verification, Tester Failure Debugs, ASIC Flow Understanding, Team Working Skills, Analytical Skills, Problem Solving Skills, Scripting Skills, PERL, TCL, Python, Self-Motivated, Multitasking, Diversity

Industry

Semiconductor Manufacturing

Description
Experienced in generating top-level functional vectors for IPs used in production and characterization testing. Experience with SOC level verification. Experience in Tester failure debugs. ASIC flow understanding. The ability to work as an individual and as part of a team to deliver complex SoCs starting from the creation of the vectors, verification, and Post silicon debug. In addition, be self-motivated with the initiative to seek constant improvements in the DFT design methodologies. The candidate must also possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment. Scripting skills such as PERL/TCL/Python are preferred. 10+ years of in DFT implementation, verification and post silicon debug areas. We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Responsible for generating top-level functional vectors for IP's for production and Char testing.

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Responsibilities
Responsible for generating top-level functional vectors for IPs used in production and characterization testing. Deliver complex SoCs starting from the creation of the vectors, verification, and post-silicon debug.