Senior Staff Engineer - Design Verification- SerDes/ PHY/AMS / Mixed‑Signal at Marvell Technology

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

07 Aug, 26

Salary

0.0

Posted On

09 May, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

SystemVerilog, UVM, SerDes, PHY Architectures, AMS, Mixed-Signal Design, Register Modeling, Verification IPs, Regression Management, Coverage Analysis, Link Training, Calibration Logic, DSP-Analog Interaction, GLS, Low-Power Verification, Post-Silicon Debug

Industry

Semiconductor Manufacturing

Description

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Central Engineering AMS IP delivers high quality analog and mixed signal IP and verification for Marvell’s advanced IPs, SoCs and platforms. The team provides scalable, reusable solutions across high speed interfaces (SerDes, DDR, D2D, PCIe, Ethernet PHY components) and advanced process nodes (5nm, 3nm, 2nm), enabling first time right silicon, reduced integration risk, and faster time to market through strong design verification convergence and system level validation. What You Can Expect Education: Bachelor’s or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5 to 9 years of experience. in verification and/or AMS/mixed‑signal design environments. • Strong hands‑on experience with SystemVerilog and UVM. • Working knowledge of: • SerDes or PHY architectures • AMS / mixed‑signal concepts • Register modeling and firmware interaction • Experience integrating or using verification IPs (VIPs). • Ability to debug issues across multiple abstraction layers with guidance. • Familiarity with regression management and coverage analysis. Behavioral & Growth Expectations • Demonstrates strong ownership of assigned verification areas. • Executes tasks independently with attention to quality and detail. • Communicates progress, issues, and technical findings clearly to the team. • Actively seeks to deepen domain knowledge and technical breadth. • Willingness to learn from senior engineers and accept feedback. • Begins contributing beyond tasks by suggesting incremental improvements to testbenches, checks, or flows. Nice‑to‑Have / Growth Differentiators • Exposure to AMS verification tools and modeling techniques. • Experience with link training, calibration logic, or DSP‑analog interaction. • Basic exposure to GLS, low‑power verification, or post‑silicon debug. • Interest in automation, scripting, or productivity improvements. What We're Looking For The Staff Engineer is a hands‑on verification engineer responsible for driving block‑ and subsystem‑level verification of AMS and high‑speed SerDes IPs. This role emphasizes execution excellence, technical rigor, and ownership, with opportunities to grow into broader technical leadership over time. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Interview Integrity To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews. These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-RV1 Join our talent community to hear about company news, job openings and events. Join our Talent Community! Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Recruitment fraud is a well-known way that third parties try to get personal information or to steal money from you. Please review Marvell’s guidance here to learn more on how you can protect yourself.

Responsibilities

The role involves driving block- and subsystem-level verification of AMS and high-speed SerDes IPs. The engineer is responsible for ensuring first-time right silicon through strong design verification convergence and system-level validation.