Senior Staff Engineer Mixed Signal Verification at Infineon Technologies AG Australia

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

23 Mar, 26

Salary

0.0

Posted On

23 Dec, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

AMS Verification, Cadence Tools, Synopsys Tools, Mentor Tools, Verilog HDL, Behavioral Modeling, SV, UVM, Analog Circuit Basics, Test Plan Preparation, Debugging, Project Leadership, Scripting Languages, Mixed Signal Design, Power Management, Data Converters

Industry

Semiconductor Manufacturing

Description

Candidate should have working experience with AMS Verification on multiple SOC’s or sub-systems. One should have proficiency in AMS simulation environment using Cadence/Synopsys/Mentor tools. Knowledge of digital design techniques, Verilog HDL, and standard RTL coding styles, as well as analog circuit basics, with previous analog design experience a plus. Candidate should be familiar with the concepts of behavioral modeling - both digital (Verilog-D) and analog (Verilog-A or Verilog-AMS). Experience in SV and UVM testbench development/modifications from mixed signal perspective is a plus. Functional knowledge of analog and mixed signal building blocks, such as comparators, op-amps, switched cap circuits, various types of ADCs and DACs, current mirrors, charge pumps, and regulators is expected. Working knowledge of Perl / Skill/ Python/Tcl or other scripting relevant language is a plus. Candidate should have ability to lead a project team, and work collaboratively in a multi-site development environment. Job Description In your new role you will: Behavioral modeling: Verilog, Wreal or SV-RNM -Full AMS Verification for SoC or IPs -Full Test plan preparation as per the dynamics of product specifications - Full Dealing challenges with AMS methodologies of Cadence: irun/xrun or Synopsys: XA-VCS or Mentor Eldo ADMS -partial Testcase Debug & proposing new scenarios - Partial Handling project dynamics on scope, schedule and effort – coming up with alternative verification plans, Mentoring Junior engineer – Partial Ability to lead MSV projects independently Drive enhancements in known methodologies Your Profile You are best equipped for this task if you have: Bachelors with 5+ years or Masters with 4+ years of experience Analog: functional spec understanding of standard power management blocks, clock circuits and data converters. Loop analysis is an added advantage HDL/HVL: Verilog/Verilog-ams, SV/UVM added advantage Tools: Cadence Xcelium + spectre/ Synopsys XA-VCS/ Mentor Eldo ADMS Automation: Perl/python/shell Schedule and result oriented execution mindset, flexible in working as per the project scope needs, Exploring and experimentation for continuous methodology improvements Ability to drive projects and debug independently. Contact: swati.gupta@infineon.com #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.

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Responsibilities

The candidate will be responsible for AMS verification for SoCs or IPs, including behavioral modeling and test plan preparation. They will also handle project dynamics and mentor junior engineers.