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Senior Staff Engineer Physical Design (f/m/div) at Infineon Technologies AG Australia

Graz, Styria, Austria -

Full Time

Start Date

Immediate

Expiry Date

12 Feb, 26

Salary

0.0

Posted On

14 Nov, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Physical Design, SoC Design, EDA Tools, Power Routing, Layout Verification, Semiconductor Manufacturing, Design Rules, EMIR Analysis, Problem-Solving, Analytical Skills, Communication Skills, Team Collaboration

Industry

Semiconductor Manufacturing

Description

We are seeking a talented and experienced Senior Staff Physical Design Engineer to join our System-on-Chip (SoC) team in Graz. In this role, you will be responsible for various aspects of physical design, from IP integration to power routing and layout verification. The ideal candidate will have a strong background in SoC design and a passion for creating cutting-edge semiconductor solutions. Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field 5+ years of experience in physical design for SoCs Proficiency in industry-standard EDA tools for physical design and verification Strong understanding of semiconductor manufacturing processes and design rules Experience with power routing and EMIR analysis Excellent problem-solving and analytical skills Strong communication skills and ability to work in a collaborative team environment We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. IP Integration and Optimization: Integrate IPs in SoC Toplevel designs

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Responsibilities

The Senior Staff Physical Design Engineer will be responsible for various aspects of physical design, including IP integration and power routing. The role involves layout verification and creating cutting-edge semiconductor solutions.