Senior Staff Engineer, Serdes Layout Design at SAMSUNG AUSTIN SEMICONDUCTOR LLC

San Jose, California, United States -

Full Time

Start Date

Immediate

Expiry Date

26 Jan, 26

Salary

289050.0

Posted On

28 Oct, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Serdes Layout Design, High Speed Mixed-Signal Layout, Analog Layout, Sub-Micron CMOS Technologies, Chip Level Design, DRC, LVS, Virtuoso, Calibre, SkillCad, Communication Skills, Project Leadership, Programming Knowledge, Curiosity, Collaboration, Innovation

Industry

Semiconductor Manufacturing

Description

Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World’s Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities. Samsung Semiconductor Inc. (SSI) is advancing the world’s technology. As a leader in Memory, System, LSI and LCD technologies, our US teams contribute to breakthroughs in 5G, SOC, memory and display. With our global perspective and diversity of thought, we proudly serve our customers around the world. We are looking for team members who share our commitment to learning and growth and excel when collaborating within and across teams. Location: Daily onsite presence at our San Jose, CA headquarters in alignment with our Flexible Work policy What You’ll Do As a senior high speed mixed-signal layout/analog layout engineer, you will be working with circuit designers located in San Jose, California, USA to accomplish layout tasks. Circuits that you will need to work on includes High Speed RX (receiver), TX (transmitters), PLL, CDR, Analog reference circuits, and so on. You should have experiences doing layout with sub-micron CMOS technologies, You’ll work with designers to optimize the performance and power consumption of SERDES analog PHY. Location: Daily onsite presence at our San Jose, CA headquarters in alignment with our Flexible Work policy Working with remote circuit designers to determine the chip floorplan. You need to come up with strategies to optimize the parasites, reduce area, and improve High Speed SERDES/analog performance. You need to be able to estimate schedule and come up with plan how to get things done within a dedicated time frame. You should be able to read the design document provided by the foundry and figure out how to resolve issues like latch-up and DRC. Perform custom layout using Virtuoso, and be able to get LVS/DRC clean. You should be familiar with CAD tools, including Virtuoso, Calibre LVS, DRC, SkillCad and so on. Desired to have experience on chip level design, like bump, pad, and ESD strategies. Good communication skills to discuss with circuit designer. What You Bring Bachelors with 15+ years, Masters with 13+ years or PhDs with 10+ years of experience. Experience in RF/analog/mixed-signal/serdes layout design of deep submicron CMOS circuits and recent experience on advance nodes including FinFET and GAA technologies High level of proficiency in interpretation of CALIBRE DRC, ERC, LVS, reports Familiar with analog/mixed-signal related circuit layout, including high-speed I/O block such as comparator/transmitter/receiver/PLLs and so on. Experience with CADENCE or MENTOR GRAPHICS layout tools Good communication skills with design leads as well as engineers for schedule planning Experience of leading a complicated layout project, and tape-out successfully. Programming knowledge in SKILL, Perl, and/or Python is a bonus You’re inclusive, adapting your style to the situation and diverse global norms of our people. An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. You’re collaborative, building relationships, humbly offering support and openly welcoming approaches. Innovative and creative, you proactively explore new ideas and adapt quickly to change. #LI-VL1 What We Offer The pay range below is for all roles at this level across all US locations and functions. Individual pay rates depend on a number of factors—including the role’s function and location, as well as the individual’s knowledge, skills, experience, education, and training. We also offer incentive opportunities that reward employees based on individual and company performance. This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours. Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community. Enjoy Time Away You’ll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge. Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and an errand service. Prioritize Emotional Wellness With on-demand apps and paid therapy sessions, you’ll have support no matter where you are. Stay Fit Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier. Embrace Flexibility Benefits are best when you have the space to use them. That’s why we facilitate a flexible environment so you can find the right balance for you. Base Pay Range $180,950—$289,050 USD Equal Opportunity Employment Policy Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations. Recruiting Agency Policy We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings. Applicant AI Use Policy At Samsung Semiconductor, we support innovation and technology. However, to ensure a fair and authentic assessment, we prohibit the use of generative AI tools to misrepresent a candidate's true skills and qualifications. Permitted uses are limited to basic preparation, grammar, and research, but all submitted content and interview responses must reflect the candidate’s genuine abilities and experience. Violation of this policy may result in immediate disqualification from the hiring process. Applicant Privacy Policy https://semiconductor.samsung.com/about-us/careers/us/privacy/

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Responsibilities

As a senior high speed mixed-signal layout/analog layout engineer, you will work with circuit designers to accomplish layout tasks for various circuits. You will optimize performance and power consumption of SERDES analog PHY and resolve layout issues.