Senior Staff Engineer-STA(Synthesis) at Infineon Technologies AG Australia

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

17 Mar, 26

Salary

0.0

Posted On

18 Dec, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Digital Designs, Synthesis, Static Timing Analysis, Power Analysis, Logic Equivalence Check, Timing Sign-off, STA Flow Development, Design Margins, Tcl, Perl, EDA Tools, Mentoring, Analytical Skills, Communication Skills, Collaboration, Constraint Mode Merging

Industry

Semiconductor Manufacturing

Description

Write and implement block level and top-level constraints for Synthesis, Static Timing Analysis. Job Description In your new role you will: Implement high-performance, low-power, and area-efficient digital designs. Write and implement block level and top-level constraints for Synthesis, Static Timing Analysis. Optimize designs for power, performance, and area, and meet PPA goals. Power analysis using PT-PX or equivalent flow. Logic Equivalence Check (LEC) and Low Power Checks (CLP) at block and SoC level designs. Define and evaluate constraints and signoff Test/DFT mode timing requirements. Knowledge on Power analysis and PT-PX flow Your Profile You are best equipped for this task if you have: Bachelors or Masters in Electrical/Electronics Engineering with 8+years of relevant experience. Delivery oriented, Passionate to learn and explore, Transparent incommunication, Flexibility related to project situations. Candidate should have strong Synthesis/STA fundamentals. Has done timing sign-off including timing margin calculations independently, hands-on STA lead of projects. Experience in handling STA of multi-power domain designs & constraint mode merging. STA flow development, abstraction with bottleneck identification. Proficient in design margins and SDC constructs. TAT reduction in multi-mode, multi power domain/designs. Generate timing ECOs for Physical design. Drive ambitious schedules and enables dependent teams to accomplish. Interface to design team and PD team and drive TAT reduction for PD. Has experience in mentoring junior engineers. Proficient with EDA tools from Synopsys/Cadence. Excellent analytical & communication skills. Shown ability to collaborate in a multi-functional environment,cross-site or cross-time zone. Proficient in Tcl and Perl or other scripting relevant language is a plus. Contact: swati.gupta@infineon.com #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.

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Responsibilities

The role involves implementing high-performance, low-power digital designs and writing constraints for synthesis and static timing analysis. Additionally, the engineer will optimize designs for power, performance, and area while ensuring compliance with timing requirements.