Senior Staff Engineer Verification (f/m/div) at Infineon Technologies AG Australia

Bristol, England, United Kingdom -

Full Time

Start Date

Immediate

Expiry Date

07 Apr, 26

Salary

0.0

Posted On

07 Jan, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

System Verilog, UVM, Functional Coverage, Test Bench Development, Debugging, Time Management, Communication, Attention to Detail, Verification Strategy, EDA Tools, IP Verification, Random Testing, Design Specifications, Test Bench Qualification, Collaboration, Ownership

Industry

Semiconductor Manufacturing

Description

#WeAreIn for jobs that impact everyone's life. What if your ideas could change the way the world connects, powers up, or thinks? As a Senior Staff Verification Engineer on our Research & Development team, you'll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life. Are you in? Your Role Key responsibilities in your new role Develop a deep understanding of complex IPs and take end-to-end ownership of the verification of these IPs Be responsible for developing System Verilog - UVM test bench environment for IPs and for developing new SV UVM verification components Be responsible for defining and writing a functional coverage model, write constrained random tests to randomly hit coverage targets Ensure the test bench meets sign-off targets, including coverage, functional safety, and test bench qualification Work on debug failing test cases to root cause Represent verification perspective and collaborate in Design and Concept meetings, contributing to enhancing the Verification strategy and architecture of IP test benches Proactively help increase the efficiency of verification activities and mitigate risks early Your Profile Qualifications and skills to help you succeed Demonstrate excellent time management skills, able to deliver high-quality results, even under pressure. Have a proven ability to communicate issues and progress clearly and effectively, ensuring transparency and collaboration within the team. Shows a great attention to detail, as precision and accuracy are key to meeting our standards of excellence. A Bachelor's degree in Electrical/Electronic Engineering or equivalent degree At least 7-8 years of experience working in Verification, preferably at the IP level, with System Verilog - UVM Advanced knowledge in UVM and SVAs, System Verilog Experience with Verification platform and framework development Proven experience of ownership of IP verification including delivering to metric targets Capability to understand complex Design specifications, derive features and test bench architectures from concept as well as capability to use industry-standard EDA tools Fluency in English (mandatory) Please send us your CV in English. Contact: Rita Costa, LinkedIn #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels. We look forward to receiving your resume, even if you do not entirely meet all the requirements of the job posting. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.

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Responsibilities

The Senior Staff Verification Engineer will develop a deep understanding of complex IPs and take end-to-end ownership of their verification. Responsibilities include developing a System Verilog - UVM test bench environment, defining functional coverage models, and collaborating in design meetings.