PREFERRED EXPERIENCE:

• Have a good understanding of various Organic/PCB technologies in order to interpret/negotiate layout guidelines
• Package/PCB layout experience. Experience in high power, Gbs IO products is a plus.
• Current working Knowledge of Cadence package design tool is a must. knowledge of SKILL is a plus.
• Working knowledge of 2D/3D package design and modeling tools, such as Cadence, Ansys, AutoCAD etc.
• Knowledge on DoE, DFM/DFR is a plus.
• Good knowledge of SerDes design and package/PCB layout constraints
• Mentor junior package designers in the group

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
Responsibilities:

THE ROLE:

The AMD Adaptive and Embedded Computing Group is seeking an experienced and self-motivated package design engineer. As a key member of the Package/Board group, you will work across chip, technology and systems teams to define cost effective and high performance solutions.

KEY RESPONSIBILITIES:

• Use Cadence tools for design, modeling and simulations. Enable timely closure of designs by getting involved with pre-design negotiations with chip/system teams and take it to design sign off
• Use analytical and simulation tools to define package/module design requirements (technology, stackup etc) in the project conception stages and negotiate with chip/system teams on product specification.
• Conduct routing, stack-up & component placement studies in addition to completing the package design activities. Translate requirements (Design guidelines, technology, stackup, manufacturing time etc) for various device packaging.
• Tradeoff PCB Layout guidelines/features to optimize the package ballmap and work with chip team to optimize the die size
• Develop multi-signal package/module models over 50 GHz bandwidth and suitable test structures for model to measurement correlation.
• Come up with performance metrics for organic package technologies in order to design high speed chips and systems
• Performing Power Integrity analysis for core as well as IO and generate power delivery network requirements with emphasis on model to measurement correlation
• Develop scripts for checking package parameters across device families, maintain a database of electrical design guidelines and rules for IO and PDN package layout implementations.