Senior Staff Physical Design Engineer at Advanced Micro Devices, Inc

George Town, Penang, Malaysia -

Full Time

Start Date

Immediate

Expiry Date

24 Jun, 26

Salary

0.0

Posted On

26 Mar, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Static Timing Analysis, Timing Closure, ECOs, Logic Equivalence Check, Low-Power Structural Checks, Physical Integrity Signoff, DRC/LVS, IR Drop, EM Analysis, Clocking, Physical Implementation, Signoff Strategy, TCL, Shell, Python, Perl

Industry

Semiconductor Manufacturing

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: We are looking for an adaptive, self-motivative physical design engineer to join our team. As a key contributor, you will be part of an engineering team to drive and improve AMD's abilities to deliver the MI/Navi series of GPU products to market. The Physical Design Engineering team, as part of GPU Engineering SoC team, furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for cutting-edge semiconductor technology, digital design, and physical design in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Responsibilities may include a subset of the following topics: Static Timing Analysis (STA) across MMMC scenarios: Driving timing closure at block and full‑chip levels, resolving violations through ECOs, constraint refinements, and reviewing SoC and block‑level signoff readiness. Lead timing signoff (setup, hold, OCV, AOCV/POCV, SI, CDC interfaces) across all modes and corners Logic Equivalence Check (LEC) for all blocks and full‑chip: Executing equivalence verification between RTL, synthesis, and P&R databases Low‑power structural checks (UPF/CLP): Ensuring correctness of power‑intent implementation, power‑domain crossings, isolation/retention, and coverage of low‑power signoff flows. Physical Integrity Signoff: Overseeing DRC/LVS structural verifications, and ensuring designs adhere to foundry signoff rules. Perform and review IR drop, EM, and power integrity signoff Clocking and top‑level mesh implementation and signoff. Own and drive block-level and/or full-chip physical implementation and signoff to tape-out Analyze complex cross-block and top-level signoff issues and define closure strategy Define and enforce signoff criteria, methodologies, and best practices Partner with PD implementation teams to guide ECO strategy for timing, power, and physical fixes Identify risk areas early and proactively drive mitigation plans Mentor senior and junior engineers; act as escalation point for signoff issues Support post-silicon analysis and correlation (as required) PREFERRED EXPERIENCE: Strong experience and specialization in deep‑submicron ASIC physical design, including all phases from RTL-to-GDSII and signoff. Proven record of Physical Design signoff flow Hands-on experience with industry-standard EDA tools (e.g., Cadence Innovus, Tempus, PrimeTime, Fusion Compiler, Calibre). Excellent scripting skills in TCL, Shell, Python, or Perl to enhance PD flows and automation. Proven ability to work with cross-functional teams across multiple sites/time zones. Strong analytical, problem-solving, and communication skills. Familiarity with CPU and or GPU architecture Proficiency in data analysis and interpretation LOCATION: Penang, Malaysia RTG #LI-KL1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Responsibilities

Key responsibilities involve driving timing closure across MMMC scenarios, leading timing signoff, and executing Logic Equivalence Check for all blocks and the full chip. The role also includes overseeing physical integrity signoff, performing IR drop/EM analysis, and owning block-level and/or full-chip physical implementation to tape-out.