SKILLS & EXPERIENCE

• 7 + years of industry experience designing production CMOS PLLs, CDRs or other precision clock generators.
• Demonstrated success achieving sub‑100 fs rms jitter and < –80 dBc reference‑spur performance at multi‑GHz frequencies.
• Mastery of analog/RF EDA tools for schematic capture, SPICE‑/S‑parameter simulation, layout, parasitic extraction and mixed‑signal verification.
• Deep understanding of phase‑noise theory, loop‑dynamics, supply‑noise coupling, clock‑tree deskew and electromagnetic crosstalk.
• Bachelor’s degree in Electrical Engineering (or related); Master’s / PhD preferred.
• Excellent problem‑solving, communication and cross‑disciplinary collaboration abilities.
• Thrive in rapid‑iteration, high‑ownership environments; bring a portfolio of patents, publications or personal projects that showcases innovative clock‑generation or high‑speed analog design.

THE ROLE

We’re searching for a Senior/Staff Analog Design Engineer with a strong focus on CMOS phase‑locked loops (PLLs) and clock‑distribution networks. You will architect, design and bring to production an ultra‑low‑jitter clocking subsystem that fans out precise multi‑GHz clocks to more than 100 parallel optical‑compute channels inside the OTPU. The work spans fractional‑N synthesisers, on‑chip loop filters, de‑skew circuits and high‑integrity clock‑tree distribution—all while meeting stringent power, spur and phase‑noise budgets required by next‑generation AI workloads.

RESPONSIBILITIES

• Architect, design and verify wide‑bandwidth fractional‑N PLLs (multi‑GHz output) including VCOs, charge pumps, loop filters and frequency dividers to achieve sub‑100 fs rms integrated jitter.
• Develop clock‑distribution networks—buffer trees, deskew circuits, differential or CML fan‑outs—that deliver phase‑aligned clocks to > 100 destination blocks with < 5 ps channel‑to‑channel skew.
• Co‑optimise the PLL with packaging, board, and power‑delivery teams to minimise supply‑induced jitter, crosstalk and electromagnetic coupling in a dense optical‑compute environment.
• Create behavioural and transistor‑level models (Verilog‑A / SPICE) for system‑level co‑simulation of timing budgets, ensuring reliable link margins across PVT corners.
• Drive post‑layout extraction, Monte‑Carlo analysis, and silicon bring‑up—including on‑wafer phase‑noise measurements, jitter transfer curves, and clock‑tree eye diagrams.
• Mentor junior engineers, lead rigorous design reviews, and champion best‑practice methodologies for low‑jitter analog design and measurement.
• Track and inject into the team the latest advances in PLL architectures, adaptive biasing, clock‑mesh techniques, and on‑chip jitter‑monitoring.