Senior/Staff Process Quality Engineer at Micron Technology

Boise, Idaho, United States -

Full Time

Start Date

Immediate

Expiry Date

19 Mar, 26

Salary

0.0

Posted On

19 Dec, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Process Quality Engineering, FOUP Environment Control, Statistical Process Control, Data Analysis, Wafer Contamination, Process Integration, Equipment Engineering, Materials Science, Chemical Engineering, Semiconductor Manufacturing, DRAM Process, Logic Process, Analytical Instrumentation, Copy Exact, Copy Smart, Yield Improvement

Industry

Semiconductor Manufacturing

Description

Lead the development of the FOUP Environment Control (FEC) program for ID1 HVM greenfield fab startup, ensuring full system readiness. Partner with engineering teams to define FEC system enablement scope, align partners, secure resources, lead multi-functional meetings, and drive successful system activation. Drive development and execution of FEC system Copy Exact/Copy Smart strategies as appropriate. Supervise production lines for yield issues potentially caused by wafer or process-related contamination and collaborate with Process Integration and Process & Equipment Engineering teams to design and implement experiments for resolution. Partner with vendors to evaluate new hardware and FOUP solutions, while aligning with internal team members to define and drive the roadmap for Fab4 HVM FOUP strategy. Assess risks and establish tool-sharing protocols between Fab4 TD and Fab4 HVM (ID1) through collaboration with key partners. Own the New Materials Integration (NMI) business process for TD materials, collaborating closely with fab partners including Process Development, Process Integration, Equipment, and Area Manufacturing Engineering teams. Bachelor's or Master's degree in Materials Science & Engineering, Chemical Engineering, Chemistry, or a closely related subject area. 3-8 years of hands-on experience in semiconductor manufacturing as a Process Module Development Engineer or Process Integration Engineer. In-depth expertise in DRAM or Logic process areas (such as Dry Etch, Thin Film Deposition, Photolithography, Wet Clean, CMP, and Metrology), with broad familiarity with the equipment used in these domains. Strong grasp of wafer and process-related contamination mechanisms across various process areas, and their effects on yield and product quality. Advanced skills in Statistical Process Control (SPC), including real-time fab data analysis and reporting, with proficiency in JMP for data visualization and analytics, plus deep knowledge of analytical instrumentation and its performance characteristics PhD in Materials Science, Chemical Engineering, Chemistry, or a related science/engineering field. Semiconductor HVM experience in FOUP Environment Control to enhance process quality and improve wafer yield.

Responsibilities

Lead the development of the FOUP Environment Control program for a greenfield fab startup, ensuring system readiness and successful activation. Collaborate with engineering teams and vendors to evaluate new hardware solutions and drive the roadmap for FOUP strategy.