Senior System Architect – Ethernet PHY & High-Speed Interconnect (m/f/d) at Huawei Technologies Co. Ltd. - Germany

Munich, Bavaria, Germany -

Full Time

Start Date

Immediate

Expiry Date

26 Sep, 26

Salary

0.0

Posted On

28 Jun, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Ethernet PHY Architecture, High-Speed Interconnect, SerDes System Architecture, Channel Modelling, Equalization, Signal Integrity, Python, MATLAB, IEEE 802.3, System-Level Simulation, Jitter Analysis, Noise Analysis, Data Converter Constraints, Technical Leadership, Standards Development, Wireline Communication

Industry

Telecommunications

Description

Huawei Heisenberg Research Center (Munich) drives advanced research and innovation in next-generation communication technologies, combining system architecture, modeling, and strategic engineering to shape future products and contribute to industry direction and standards. The Applied Network Technology Lab (ANTL) in Munich is expanding its research activities in next-generation Ethernet and high-speed interconnect technologies for data center networks. A key focus area is the physical layer (PHY), where increasing data rates introduce new challenges in signal integrity, non-linearities, and system-level optimization. We are looking for an experienced architect who can bridge deep technical analysis with long-term technology strategy, translating complex system behavior into scalable architectural solutions that will influence future products and industry standards. This is a highly influential role operating at the intersection of system architecture, advanced modelling and standards development. Join the ANTL Ethernet Team as a Senior System Architect (m/f/d) Your mission Define and and employ end-to-end PHY system models for architecture decision, covering channel behavior, TX/RX impairments, data converter constraints and associated non-idealities. Lead architecture trade-off studies across performance, power, bandwidth, BER, latency and implementation feasibility. Evaluate equalization and signal processing techniques under realistic system limitations and hardware impairments. Translate complex simulation results, impairment analysis and implementation constraints into clear, data-driven architectural recommendations and engineering insights. Define system-level constraints, performance budgets and identify optimization opportunities for future Ethernet PHY architectures. Monitor emerging Ethernet technologies and analyze standards, including IEEE 802.3, UEC, OIF and MSA activities, to identify opportunities for innovation. Shape technical positions and contribute to industry standards discussions through robust technical analysis. Provide technical leadership, architecture guidance and mentorship to engineers across multidisciplinary teams. Collaborate with universities, research institutes and external partners to help shape future PHY concepts. Your profile/areas of expertise Essential Master's degree and/or PhD in Electrical Engineering, Electronic Engineering, Computer Science or a related discipline. Strong experience with high-speed PHY, SerDes system or wireline communication system architecture. Solid understanding of Ethernet PHY architecture, including channel modelling, equalization, jitter, noise analysis and system-level data converter impact on link performance. Proficiency in Python, MATLAB or similar system-level simulation environments for architecture exploration and trade-off analysis. Ability to abstract complex physical phenomena into accurate and actionable system models and architecture trade-offs. Proven ability to make architecture decisions under technical uncertainty and clearly communicate assumptions, risks and trade-offs. Excellent communication and collaboration skills in international environments. Full professional proficiency in English. Preferred Experience with ≥100Gb/s per lane systems. Familiarity with IEEE Ethernet standards activities, UEC, OIF and MSA ecosystems, including how standards decisions influence PHY architecture choices. Experience contributing to standards discussions, technical papers or industry forums. German and/or Chinese language skills. Some international travel will be required as part of the role. By applying to this position, you agree with our Recruitment Privacy Statement. You can read in full our privacy policy here. Why join us? Influence the future direction of Ethernet and AI data center networking technologies. Shape system architectures and contribute to industry standards. Work on long-term research challenges with global impact. Collaborate with leading universities, research institutes and international experts. Operate at the intersection of research, architecture and real-world technology deployment. Our diverse and welcoming environment is shaped by different backgrounds and around 40 individual nationalities. Self-responsible work in a competent, motivated and constantly growing team. We offer healthy meals ranging from traditional Chinese to western delicacies in our famous company canteen. To keep your development ongoing, you will find a broad range of training opportunities. Many online and face-to-face training programs incl. language courses in German and Mandarin. Please send your application and CV (incl. cover letter and reference letters) in English. Huawei is a leading global information and communications technology (ICT) solutions provider. Our ICT solutions, products and services are used in more than 170 countries and regions, serving over one-third of the world's population. With 208,000 employees, Huawei is committed to develop the future information society and build a Better Connected World.

Responsibilities

Define end-to-end PHY system models and lead architecture trade-off studies to optimize performance, power, and latency for next-generation Ethernet. Influence industry standards and provide technical leadership to multidisciplinary teams and external research partners.