Senior Technologist, ASIC Development Engineering (IO Design) at Sandisk

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

29 Jan, 26

Salary

0.0

Posted On

31 Oct, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Analog Mixed Signal IPs, High-Speed Parallel PHY, NAND Flash Memory Controllers, Cross-Functional Team Interaction, High-Speed Interface Design, TX and RX Design Architectures, SERDES, Equalization Schemes, ESD Circuits Design, Custom High Speed Data Path Design, Cadence Virtuoso, Mixed-Mode Simulation, CMOS Process, FINFET Technologies, Problem Solving, Mentoring

Industry

Semiconductor Manufacturing

Description

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Developing best-in-class architecture for Analog Mixed Signal IPs and high-speed parallel PHY interface solutions for next generation NAND flash memory controllers in advanced CMOS technology nodes. Interact with cross-functional teams to define requirements/specs, conceive the optimal solution by evaluating architectures, drive implementation, closely work with layout designers in guiding and reviewing the layouts, ensure timely and high-quality deliverables, extend SOC integration support and review and provide support for post-silicon activities from IP characterization to yield improvement and RMA. Provide good technical leadership in problem solving, planning and mentoring junior and senior engineers. Propose innovative design solutions and design methodologies. Fostering innovation culture and developing efficient processes by adopting state-of-the-art technologies. Qualifications Must have • Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering • Working experience (20+ years) in IO including 5+ years as a project leader • Should have architected and lead high speed interface design solutions from specification through Silicon debug and characterization • Should have hands-on experience in TX and RX design architectures for high speed applications such as DDR4/DDR5/LPDDR4/LPDDR5 along with timing budget analysis. • Should be experienced in high speed design architectures such as SERDES, Equalization schemes • Should have hands-on experience in IPs such as SSTL, LVDS, I2C, POD IOs, PVT calibration, HV tolerant and Fail-safe IOs, Crystal oscillator etc. • Should have extensive experience in ESD circuits design, Associated ESD guidelines and recommendations in different process nodes, IO and SOC level ESD review and signoff • Experience in full custom high speed data path design such as DDR PHY will be of advantage. • Conversant with tools such as Cadence Virtuoso/Synopsys custom compiler/Hspice/Spectre/Finesim including statistical simulation methodologies • Experience in Mixed-mode simulation and analog/digital co-simulation will be of added advantage. • Experience in creating EDA model such as Verilog model, Liberty etc will be of added advantage. •Should have deep understanding and working knowledge of CMOS process including FINFET technologies such as 16nm/7nm/5nm and the associated DFM issues. • Very analytical in nature and able to work in a multi-disciplinary environment • Creative, out-of-the-box thinker with a high level of personal involvement • Strong theoretical background with a pragmatic approach. •Good verbal and written communication skills and experience working with different geographies. • Good mentoring, documentation and presentation skills Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [email protected] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.

Responsibilities

Develop best-in-class architecture for Analog Mixed Signal IPs and high-speed parallel PHY interface solutions. Interact with cross-functional teams to define requirements, drive implementation, and support post-silicon activities.