Senior Technologist, Hardware Development Engineering - at Western Digital

Roseville, California, United States -

Full Time

Start Date

Immediate

Expiry Date

12 Aug, 26

Salary

235400.0

Posted On

14 May, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Board-level Hardware Design, ASIC Integration, Signal Integrity, Power Integrity, PCIe Gen 6, 100G/200G Ethernet PAM4, FPGA Board Design, Schematic Design, EMI/EMC, DFT Strategy, Analog Circuit Design, High-speed Link Validation, Cadence, Altium, S-parameters, Root-cause Debugging

Industry

Computer Hardware Manufacturing

Description

Company Description At Western Digital, our vision is to power global innovation and push the boundaries of technology to make what you thought was once impossible, possible. At our core, Western Digital is a company of problem solvers. People achieve extraordinary things given the right technology. For decades, we’ve been doing just that. Our technology helped people put a man on the moon. We are a key partner to some of the largest and highest growth organizations in the world. From energizing the most competitive gaming platforms, to enabling systems to make cities safer and cars smarter and more connected, to powering the data centers behind many of the world’s biggest companies and public cloud, Western Digital is fueling a brighter, smarter future. Binge-watch any shows, use social media or shop online lately? You’ll find Western Digital supporting the storage infrastructure behind many of these platforms. And, that flash memory card that captures and preserves your most precious moments? That’s us, too. We offer an expansive portfolio of technologies, storage devices and platforms for business and consumers alike. Our data-centric solutions are comprised of the Western Digital®, G-Technology™, SanDisk® and WD® brands. Today’s exceptional challenges require your unique skills. It’s You & Western Digital. Together, we’re the next BIG thing in data. Job Description We are seeking an Expert-level Hardware Engineer who is equally strong in board-level hardware design and ASIC interface / integration (I/O, package, power integrity, DFT/test, analog, and signal integrity). This is a hands-on role for a recognized subject matter expertise in delivering complex hardware from concept through production, including deep lab bring-up and root-cause complex issues, able to debug across silicon, package, and board. Qualifications REQUIRED Professional hardware engineering experience. Proven ownership of multiple complex programs through the full lifecycle: architecture → design → build → bring-up → debug → qualification → production ramp → sustaining. Demonstrated, hands-on experience spanning both: Board/system hardware design (schematic ownership, layout partnership, bring-up, debug, standards compliance, manufacturing support) ASIC I/O and integration (I/O architecture decisions, package/substrate considerations, PI/SI co-design, tape-out support, DFT/test hooks) Cutting-Edge High-Speed Interfaces Hands-on experience integrating and debugging leading-edge Ethernet and PCIe interfaces, including: 100G/200G Ethernet PAM4 transceivers (system/channel design, equalization concepts, BER/PRBS testing, standards compliance planning and test) PCIe Gen 6 (system/channel design, equalization concepts, BER/PRBS testing, standards compliance planning and test) Demonstrated ability to design and simulate high-speed links across die/ASIC package/PCB/connectors/cabling, balancing SI/PI/EMI and manufacturing constraints. FPGA Board Design Proven experience designing complex boards using cutting-edge FPGAs (e.g., high-end families with high-speed transceivers), including: Power architecture and sequencing for FPGA multi-rail systems High-speed transceiver channel design, with associated reference clock design, reset/boot/strap Bring-up and debug using vendor tools, link training, PRBS/IBERT-style testing, and lab correlation Ownership of FPGA-based platform bring-up from first power-on through high-speed link validation and system integration. AMD FPGA Knowledge preferred Board-Level Design Expert schematic design and review for high-complexity boards (compute/networking/accelerator-class or equivalent). Strong experience with: Multi-rail power distribution networks (frequency domain impedance control, sequencing, fault handling) High-speed interfaces (DDR, PCIe, Ethernet/SerDes-based links, USB, I2C, SPI, MIPI—based on product needs) Controlled impedance trace design (understanding manufacturing and cost tradeoffs) Clocking/reset/fault tolerant architectures and debug access design General analog circuit design Proven partnership with layout teams to define and enforce: Stackups, reference planes, return paths, via design and strategy, routing constraints Differential pair controlled impedance routing, channel constraints, connector strategy, manufacturability Signal Integrity (SI) & Power Integrity (PI) Across Die / Package / Board SI design experience: Insertion loss, return loss, eye/jitter concepts, electrical noise abatement, termination, discontinuities, correlation of models to measurements. Deep PI/PDN experience: target impedance approach, decap strategy, anti-resonance mitigation, transient response, measurement and correlation. Practical EMI/EMC grounding/shielding/filtering understanding grounded in design and lab realities. ASIC I/O, Package, and Power Co-Design Ability to own or co-own ASIC I/O choices: I/O standards, voltage domains, ESD strategy, drive/slew tuning, noise coupling/SSO considerations Strong understanding of package/substrate impacts: Pinout/ballout tradeoffs, escape routing constraints, lane swapping realities Package parasitics effects on SI/PI and timing margins Thermal/mechanical considerations influencing reliability and assembly Power architecture competence spanning system and ASIC-aware constraints (noise isolation, domain partitioning, bring-up hooks). DFT / Test Strategy Bridging Silicon ↔ Board ↔ Manufacturing Strong working knowledge of DFT concepts and productization: JTAG/boundary scan, scan/ATPG fundamentals, BIST/loopbacks/PRBS, on-chip monitors/telemetry Experience defining debug and manufacturing test strategy: Test access, test point strategy, coverage vs SI impact, failure analysis workflows Analog & Mixed-Signal Practical Depth Practical capability to own/review analog subsystems relevant to high-performance designs: Clock generation/distribution and jitter sensitivity Filtering/biasing, stability fundamentals, measurement integrity/noise coupling Mixed-signal partitioning and grounding strategy Hands-On Lab Debug Expectations Expert in structured bring-up and root-cause debug: Creation and execution of EVT test plan High-speed measurement competence (Oscilloscopes, BERT, network analyzers, spectrum analyzers, probing strategy, fixtures, de-embedding awareness) Ability to correlate bench measurements back to simulation and drive corrective actions Tools & Workflow Familiarity with mainstream schematic/layout environments (e.g., Cadence/Altium/Mentor-class tools) and constraint-driven design practices. Comfortable with SI/PI modeling workflows (IBIS/AMI, S-parameters, SPICE-level reasoning) and validation against lab data. Strong documentation, design review, ECO, and risk-management discipline Operates as a cross-functional technical leader across silicon, package, board, validation, test, manufacturing. Writes clear specs/constraints that prevent rework (I/O requirements, channel budgets, PDN targets, bring-up/test access). Drives design reviews that identify real risks early and mentors engineers across experience levels. Drive partnerships with key IP, component and manufacturers. Examples where you personally identified high-speed margin failures (examples: 100/200G PAM4 and/or PCIe Gen 6 or slower data rates) through SI/PI analysis or lab testing. Examples of cross-boundary root cause (ASIC ↔ package ↔ board) with measurable corrective actions. Examples where you improved observability/DFT/test hooks to accelerate bring-up and production readiness. PREFERRED Advanced packaging or multi-die systems (e.g., chiplets/interposers/HBM-class integration). Ownership of qualification/compliance (EMC, safety, thermal/mechanical) and production yield improvement. Experience with design for low cost, second-source strategies, and sustained field reliability initiatives. Salary Range 176,600.00-235,400.00 Additional Information WD is committed to providing equal opportunities to all applicants and employees and will not discriminate against any applicant or employee based on their race, color, ancestry, religion (including religious dress and grooming standards), sex (including pregnancy, childbirth or related medical conditions, breastfeeding or related medical conditions), gender (including a person’s gender identity, gender expression, and gender-related appearance and behavior, whether or not stereotypically associated with the person’s assigned sex at birth), age, national origin, sexual orientation, medical condition, marital status (including domestic partnership status), physical disability, mental disability, medical condition, genetic information, protected medical and family care leave, Civil Air Patrol status, military and veteran status, or other legally protected characteristics. We also prohibit harassment of any individual on any of the characteristics listed above. Our non-discrimination policy applies to all aspects of employment. We comply with the laws and regulations set forth in the "Know Your Rights: Workplace Discrimination is Illegal” poster. Our pay transparency policy is available here. WD thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. WD is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [email protected] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. Based on our experience, we anticipate that the application deadline will be 08/13/2026(3 months from posting), although we reserve the right to close the application process sooner if we hire an applicant for this position before the application deadline. If we are not able to hire someone from this role before the application deadline, we will update this posting with a new anticipated application deadline. #LI-TD1 Compensation & Benefits Details An employee’s pay position within the salary range may be based on several factors including but not limited to (1) relevant education; qualifications; certifications; and experience; (2) skills, ability, knowledge of the job; (3) performance, contribution and results; (4) geographic location; (5) shift; (6) internal and external equity; and (7) business and organizational needs. The salary range is what we believe to be the range of possible compensation for this role at the time of this posting. We may ultimately pay more or less than the posted range and this range is only applicable for jobs to be performed in California, Colorado, New York or remote jobs that can be performed in California, Colorado and New York. This range may be modified in the future. If your position is non-exempt, you are eligible for overtime pay pursuant to company policy and applicable laws. You may also be eligible for shift differential pay, depending on the shift to which you are assigned. You will be eligible to be considered for bonuses under either WD’s Short Term Incentive Plan (“STI Plan”) or the Sales Incentive Plan (“SIP”) which provides incentive awards based on Company and individual performance, depending on your role and your performance. You may be eligible to participate in our annual Long-Term Incentive (LTI) program, which consists of restricted stock units (RSUs) or cash equivalents, pursuant to the terms of the LTI plan. Please note that not all roles are eligible to participate in the LTI program, and not all roles are eligible for equity under the LTI plan. RSU awards are also available to eligible new hires, subject to WD's Standard Terms and Conditions for Restricted Stock Unit Awards. We offer a comprehensive package of benefits including paid vacation time; paid sick leave; medical/dental/vision insurance; life, accident and disability insurance; tax-advantaged flexible spending and health savings accounts; employee assistance program; other voluntary benefit programs such as supplemental life and AD&D, legal plan, pet insurance, critical illness, accident and hospital indemnity; tuition reimbursement; transit; the Applause Program; employee stock purchase plan; and the WD Savings 401(k) Plan. Note: No amount of pay is considered to be wages or compensation until such amount is earned, vested, and determinable. The amount and availability of any bonus, commission, benefits, or any other form of compensation and benefits that are allocable to a particular employee remains in the Company's sole discretion unless and until paid and may be modified at the Company’s sole discretion, consistent with the law. Notice To Candidates: Please be aware that WD and its subsidiaries will never request payment as a condition for applying for a position or receiving an offer of employment. Should you encounter any such requests, please report it immediately to WD Ethics Helpline or email [email protected]. Job Type (exemption status): Exempt position - Please see related compensation & benefits details below Salary Range: 176,600.00-235,400.00 Business Function: Hardware Development Engineering Work Location: Roseville California Office--LOC_WDT_USCA12

Responsibilities

Lead the end-to-end development of complex hardware from concept through production, focusing on board-level design and ASIC integration. Perform deep lab bring-up and root-cause analysis across silicon, package, and board boundaries.