Senior Technologist, Mask Design Engineering ((Extensive IC Layout Design-2 at Sandisk

Bengaluru, karnataka, India -

Full Time

Start Date

Immediate

Expiry Date

13 Sep, 26

Salary

0.0

Posted On

15 Jun, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

IC Layout Design, Analog Design, Digital Design, Mixed-Signal Design, DRC/LVS, Parasitic Extraction, EM/IR Analysis, Floorplanning, Power Distribution Networks, VLSI, Sign-off Verification, Layout Automation, Physical Constraints, Correct-by-Construction Methodology, Technical Mentorship, Cross-Functional Leadership

Industry

Semiconductor Manufacturing

Description

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Role: Mask Design Senior Technologist (Principal Engineer) Role Overview As a VLSI Layout Technologist, you will serve as a senior technical member driving full‑chip and block‑level layout architecture across Analog, Digital, and Mixed‑signal domains. Expectation is to influence design strategy, lead complex layout development, and ensure first‑pass silicon success. Key Responsibilities Advanced Layout Design & Optimization Lead the development, optimization, and integration of peripheral and core circuit layouts across Analog, Digital, and Mixed‑Signal domains. Ensure adherence to design specifications, performance targets, and foundry rules while driving correct‑by‑construction methodologies. Design Verification & Sign‑off Leadership Oversee DRC, LVS, parasitic extraction, and sign‑off flows. Ensure design integrity, manufacturability, and first‑pass silicon success through rigorous verification and closure strategies. Power Distribution & Floor planning Architecture Architect full‑chip power distribution networks and floorplans to optimize electrical performance, minimize parasitic’s , and reduce die size. Provide guidance on placement, routing, and hierarchical layout planning. Cross‑Functional Technical Leadership Collaborate with Design Engineering (DE), Integration (INTEG), and Process Technology teams across global sites to resolve design issues, align methodologies, and ensure seamless integration. Drive technical convergence on topics such as buffer topology, layout methodologies, and design‑rule interpretation. Methodology Development & Continuous Improvement Define and enhance layout methodologies, automation flows, and best practices to improve productivity, consistency, and design quality. Champion innovation in layout automation and process optimization. Technical Mentorship & Review Provide technical direction to senior layout engineers, conduct critical block reviews, and elevate team capability through mentorship and knowledge sharing. Qualifications Your Experience and Role Expectation Extensive IC Layout Expertise : 22+ years of full‑chip custom layout experience across analog, digital, and mixed‑signal designs with deep knowledge of power routing, signal planning, and physical constraints. Tool & Verification : Expert in DRC/LVS, parasitic extraction, EM/IR analysis, and sign‑off verification using industry‑standard tools. 'Floor planning Strength : Proven ability to architect efficient floorplans, optimize placement, and reduce die area using correct‑by‑construction approaches. Cross‑Site Leadership : Strong track record collaborating with multi‑site, cross‑disciplinary teams and leading small technical groups to successful design convergence. Communication & Methodology : Excellent communication skills with a proactive approach to methodology development, automation, and continuous improvement. Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [email protected] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. Job Type (exemption status): Exempt position - Please see related compensation & benefits details below Business Function: Mask Design Engineering Work Location: Bangalore PTP Office (IBP)--LOC_WDT_IBP

Responsibilities

Lead the development and optimization of full-chip and block-level layout architecture across analog, digital, and mixed-signal domains. Oversee design verification, sign-off flows, and power distribution networks to ensure first-pass silicon success.