Senior Verification Engineer at Microsoft

Raleigh, North Carolina, United States -

Full Time

Start Date

Immediate

Expiry Date

17 Mar, 26

Salary

234700.0

Posted On

18 Dec, 25

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Pre-silicon Verification, Test Plans, Simulation Environments, Debugging, Mentoring, AI, PCIe Subsystems, Formal Verification, RTL Design, Assembly, Scripting Languages, SystemVerilog, C/C++, UVM Test Benches, Chip Architecture, Python

Industry

Software Development

Description

Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state of the art custom computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantage to Microsoft and enable our customers to achieve more. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the CSME team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for a Senior Verification Engineer to join the team. Responsibilities The role will be responsible for pre-silicon functional verification, creation of verification environments and tests at the block and sub-system level, reference modeling, emulation, and post-silicon validation. Qualifications Minimum Qualifications: Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience. 4+ years of experience in developing test plans, creating simulation environments, developing tests, and debugging for multiple IPs, SoCs or systems. 2+ years of experience leading pre-silicon verification of blocks and sub systems through full cycle 2+ years of experience in mentoring individual engineers Other Requirements: Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter. Preferred Qualifications: Experience in working with AI and motivation in utilizing AI in the day-to-day work Experience with PCIe subsystems Experience with the use of formal verification methods Experience in RTL design for FPGA or emulation Experience in Assembly, startup code and linker scripts Experience in developing makefiles for software development Proficient in SystemVerilog, C/C++, and scripting languages such as Python, Ruby or Perl. In depth knowledge of verification principles, testbenches, stimulus generation. Experience with random-stimulus and coverage-based techniques along with test plan definition Substantial background in creating UVM Test Benches, developing tests, and debugging designs Solid understanding of chip and/or computer architecture Experience writing tests in C and C++ Scripting languages such as Python, Ruby, or Perl #SCHIE #CSME Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $158,400 - $258,000 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Responsibilities

The role involves pre-silicon functional verification, creating verification environments and tests at the block and sub-system level, and post-silicon validation. The engineer will also be responsible for reference modeling and emulation.