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Senior Verification Engineer at Microsoft
Hyderabad, Telangana, India -
Full Time

Start Date

Immediate

Expiry Date

24 Feb, 26

Salary

0.0

Posted On

26 Nov, 25

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

No

Skills

Verification Principles, Testbenches, Stimulus Generation, UVM, C++, Computer Architecture, Debugging RTL, Simulation, Emulation, SystemVerilog, SVA, Formal Verification, Python, Perl, Design Verification, Complex IP

Industry

Software Development

Description
The AISiE silicon team is seeking a passionate, driven, and intellectually curious computer/electrical engineer to deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge, custom IP and SoC designs that can perform complex and high-performance functions in an extremely efficient manner. Plan the verification of complex design IP/SoC interacting with the architecture and design engineers to identify verification test scenarios. Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools Develop tests using UVM or C/C++ Analyse and debug test failures with designers to deliver functionally correct design. Identify and write functional coverage for stimulus and corner cases. Close coverage to plug verification holes and meet tape out requirements. Processor based testbenches and emulation 8 or more years of experience in design verification with a proven track record of delivering complex Accelerators or CPU's or SoC IP's In depth knowledge of verification principles, testbenches, stimulus generation, and UVM or C++ based test environments. Solid understanding of computer architecture Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments Scripting language such as Python or Perl
Responsibilities
Plan the verification of complex design IP/SoC and create verification environments. Analyze and debug test failures to ensure functionally correct designs.