Senior Verification Engineer at Microsoft Nuance

, , United States -

Full Time

Start Date

Immediate

Expiry Date

26 Jun, 26

Salary

234700.0

Posted On

28 Mar, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

System Verilog, UVM, Verification Fundamentals, RTL, FPGA, SmartNICs, SDN, RDMA, Constrained Random Verification, Test Plans, Functional Coverage, CI/CD, Agile Development, Python, PowerShell, Networking Protocols

Industry

Software Development

Description

Overview Microsoft Azure is building the fastest network in public cloud. We are seeking candidates who can span the stack from hardware to systems to applications, turning ideas into production systems at a rapid pace. Join us as a Senior Hardware Engineer to build the world's fastest public cloud and make a difference to millions of people across the planet.As a Senior Verification Engineer in the Accelnet Hardware team, you will be responsible for building, testing, and deploying networking acceleration on Azure, and the largest deployment of Field-Programmable Gate Array (FPGA) SmartNICs (Azure Boost) in the world. You will develop the infrastructure for next-generation Software-Defined Networking (SDN), including arbitrary packet manipulations, reducing virtualization overhead, improving network security, enhancing connection establishment performance, and improving performance with Remote Direct Memory Access (RDMA) and custom network protocols. You should be able to drive projects with both hardware and software teams, both inside and outside of Microsoft. This is a unique opportunity for a Senior Verification Engineer to see Register-Transfer Level (RTL) code go to production within weeks instead of years. Come help build one of the few truly hyperscale global clouds with innovations possible at every level of the computing stack. Microsoft’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond. Responsibilities • Build scalable constrained random verification environment in system Verilog using prevalent verification methodologies. • Create comprehensive test plans to address functional scenarios in discussions with the software and hardware design teams. • Execute the test plan by adding testcases and tracking verification through coverage driven metrices. • Create and enhance verification environment by adding sequences, constraints, assertions, and functional coverage. • Scripts to automate and maintain execution of test suits to support continuous integration (CI) and continuous development (CD) flow. • Apply Agile development methodologies such as hosting code reviews, sprint planning, frequent deployment to cloud, and iterative development of features. • Handle occasional on-call responsibilities for addressing hardware issues reported by our customers. Qualifications Required Qualifications: Bachelor’s Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 5+ years technical engineering experience with Universal Verification Methodology (UVM), System Verilog and Verification Fundamentals OR Master’s Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 3+ years technical engineering experience with Universal Verification Methodology (UVM), System Verilog and Verification Fundamentals OR equivalent experience. 5+ years technical experience in hardware design verification, verification methodologies, or system Verilog. Other Qualifications: Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. Preferred Qualifications: Bachelor's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 8+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 6+ years technical engineering experience with hardware design verification, verification methodologies, and system Verilog. OR Doctorate Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field AND 3+ years technical engineering experience with hardware design verification, verification methodologies, and system Verilog OR equivalent experience. 8+ years of experience verifying designs at both unit and system levels, with a good understanding of constrained random verification principles and the ability to write comprehensive test plans. 1+ year(s) of experience with SystemVerilog, including constraints, functional coverage, and assertions, as well as familiarity with formal verification techniques. 1+ year(s) of experience with scripting languages such as Python or PowerShell, and knowledge of networking fundamentals including protocols like IPv4, IPv6, TCP, UDP, and DTLS. Hardware Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $158,400 - $258,000 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled. Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

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Responsibilities

The role involves building, testing, and deploying networking acceleration on Azure, focusing on FPGAs and developing infrastructure for next-generation Software-Defined Networking. Responsibilities include building scalable constrained random verification environments, creating comprehensive test plans, and enhancing verification environments with sequences and assertions.