Senior Verification Engineer at SEAKR Engineering

Centennial, Colorado, United States -

Full Time

Start Date

Immediate

Expiry Date

12 Jun, 26

Salary

165000.0

Posted On

14 Mar, 26

Experience

10 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

Verification Engineering, System Verilog, UVM, Simulation Strategies, Digital Test Plan Creation, Coverage Metrics, Regression Tests, Test Requirement Derivation, Test Environment Architecture, Failure Diagnosis, Code Coverage Analysis, Team Leadership, Modelsim/Questasim, Verilog RTL Analysis, VHDL Analysis, Ethernet Verification

Industry

Space Research and Technology

Description

Company Description Join SEAKR Engineering, a leading-edge provider of advanced electronics for space applications. Pushing the boundaries of technology on a mission to change the world for the better from space. Job Description SEAKR is currently seeking a Verification Engineer who is responsible for developing verification and simulation strategies, conducting design reviews, creating a digital test plan and providing coverage metrics. The Engineer is responsible for the construction and maintenance of simulation environments using System Verilog with UVM (Universal Verification Methodology), and performing and evaluating regression tests for a design under test. The candidate must be able to extract and derive test requirements and sequences for an interface or interfaces based on available design documentation and requirements. Ability to architect and construct full test environments for complex devices using UVM, including coverage, is required. The candidate shall be capable of diagnosing sophisticated test failures and filing results, and be capable of analyzing code coverage to adjust agent sequence behavior. Ability to provide direction to less senior verification engineers is required. Ability to lead a team of verification engineers to fully verify a device is required. Ability to use simulation tools such as Mentor Graphics Modelsim/Questasim for simulation debug and reporting is required. Ability to analyze Verilog RTL to diagnose test failures is required. Ability to analyze VHDL is a plus. Must be able to work effectively under pressure to meet tight deadlines. Experience verifying Ethernet and PCIe designs a plus. Experience using/integrating verification IP into existing environments a plus Experience verifying DSP related designs a plus. Qualifications A Bachelors degree in Electrical Engineering or Computer Science . A Master's Degree is preferred. A minimum of 10 years of verification engineering experience are required Additional Information Compensation: Base pay range is $130,000-$165,000 per year, depending on qualifications. SEAKR has very rich medical, dental and vision insurance plans, along with a generous 401(k) retirement plan. In addition to base salary, employees are eligible for a year-end bonus. SEAKR offers a variety of paid leave, such as vacation, sick, bereavement, and FMLA. Remote work is possible, however hybird is strongly preferred. SEAKR is an Equal Opportunity Employer - All your information will be kept confidential according to EEO guidelines. US Citizenship Required Applications will be accepted until 3/27/26 Compensation: USD 130000 - USD 165000 - yearly

Responsibilities

The engineer will be responsible for developing verification and simulation strategies, creating digital test plans, and providing coverage metrics, while constructing and maintaining simulation environments using System Verilog with UVM. This role also requires diagnosing sophisticated test failures, analyzing code coverage, and leading verification teams to fully verify complex devices.