Senior VLSI Process Design Engineer at Intel - Dubai

Haifa, Haifa District, Israel -

Full Time

Start Date

Immediate

Expiry Date

23 May, 26

Salary

0.0

Posted On

22 Feb, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

VLSI Physical Design, Process Technology Optimization, PPA Optimization, Experimentation, Design Methodologies, Python, TCL, Floorplanning, Placement, Routing, Timing Closure, Device Analysis, Cell Analysis, Block Analysis, Mentoring

Industry

Semiconductor Manufacturing

Description

Job Details: Job Description: About the Team Our team is dedicated to optimizing Intel's process technology to meet evolving Intel designs needs. We drive continuous improvements in silicon designs and methodologies, working at the intersection of process development and design implementation. By partnering closely with Core and SoC design teams, we capture and optimize process requirements to enable competitive, high-performance products. Role Overview As a Senior VLSI Process Design Engineer, you will play a key role in achieving best-in-class power, performance, and area (PPA) for Intel IPs. You will conduct experiments to identify challenges and optimization opportunities in Intel's process technology, evaluate device, cells and blocks, and translate findings into actionable recommendations that influence strategic decision-making and product direction. Key Responsibilities Conduct experiments to identify potential challenges and optimization opportunities in Intel's process technology. Drive continuous improvements to enhance Intel's designs and methodologies across advanced technology nodes. Define methodologies and build tools to optimize PPA of Intel IPs. Analyze PPA results, derive insights, and communicate findings and recommendations to stakeholders, contributing to strategic decision-making and project direction. Collaborate with Core and SoC design teams to capture and optimize process requirements that enable competitive designs and products. Mentor and guide technical teams, foster growth and best practices. Qualifications: BSc or MSc in Electrical Engineering or Computer Engineering. 5+ years of hands-on experience in VLSI physical design, with a proven track record of successful projects on advanced technology nodes. Basic scripting languages knowledge such as Python and TCL. Preferred Good familiarity with physical design implementation flows and techniques, including floorplanning, placement, routing, and timing closure. Knowledge at the cell and transistor level. Deep understanding of the various factors impacting PPA trade-offs. Experience mentoring technical teams. Job Type: Experienced Hire Shift: Shift 1 (Israel) Primary Location: Israel, Haifa Additional Locations: Business group: Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. * Intel’s official careers website. Find your next job and take on projects that shape tomorrow’s technology. Benefits Internships Life at Intel Locations Recruitment Process Discover your place in our world-changing work.

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Responsibilities

The engineer will conduct experiments to find optimization opportunities in process technology and drive continuous improvements in designs and methodologies across advanced technology nodes. Key tasks include defining optimization tools and analyzing Power, Performance, and Area (PPA) results to influence strategic decision-making.