Silicon Design Engineer at Advanced Micro Devices, Inc

, , China -

Full Time

Start Date

Immediate

Expiry Date

29 Jul, 26

Salary

0.0

Posted On

30 Apr, 26

Experience

5 year(s) or above

Remote Job

Yes

Telecommute

Yes

Sponsor Visa

Skills

RTL Design, Micro-architecture, Digital ASIC Design, Synthesis, Equivalence Checking, Clock-Domain Crossing Analysis, Static Timing Analysis, Area Optimization, Power Optimization, Linting, High-speed I/O Protocols, PCIe, UCIe, Digital Front-end Implementation

Industry

Semiconductor Manufacturing

Description

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: CIT (Chiplet Interconnect Technology) team delivers industry leading high-performance interconnects IP for all AMD products including Server, GPU, Client and Game consoles. CIT includes AMD Internal links as well as Industry Standard links for on-chip connections. We are searching for a designer to join the fast-growing CIT team, and be responsible for defining, specifying, and implementing current and future high-speed I/O IPs. The candidate will be involved in digital design and will be to work on the micro-architecture of leading IPs. THE PERSON: People who have the passion to work on leading edge technology, who have solid design capability and communication skills will be successful in this role. Strong team spirit Drive to completion Fluent verbal English KEY RESPONSIBILITIES: Defining and implementing the RTL of a new AMD chiplet interconnect IP Participate in RTL implementation for functional blocks of the IP Optimize RTL implementation from implementation perspective in cooperation with RTL and Architecture teams Optimization of physical implementation in cooperation with Physical Design team. Synthesis, Equivalence Checking, Clock-Domain Crossing (CDC) Analysis, Area/Power optimizations, Linting, Static Timing Analysis (STA) PREFERRED EXPERIENCE: Experience in digital front-end implementation, including micro-arch. definition Experience with state-of-the-art industry standard digital tools RTL design experience with multi-clock, high frequency designs Knowledge in digital RTL Design and Implementation Basic understanding in high-speed I/O protocols (PCIe, UCIe…) ACADEMIC CREDENTIALS: Candidate is preferred to be MSEE or BSEE with 6+ years experience in digital ASIC design. #LI-EH1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.

Responsibilities

The engineer will be responsible for defining, specifying, and implementing high-speed I/O IPs for chiplet interconnect technology. Key tasks include RTL implementation, functional block design, and collaboration with architecture and physical design teams for optimization.