Start Date
Immediate
Expiry Date
13 Mar, 26
Salary
0.0
Posted On
13 Dec, 25
Experience
2 year(s) or above
Remote Job
Yes
Telecommute
Yes
Sponsor Visa
No
Skills
Silicon Design, DFT Architecture, Scan Insertion, ATPG Pattern Generation, Gate-Level Simulation, Test Coverage Analysis, Yield Learning, Verilog RTL Design, Perl Scripting, Shell Scripting, VCS Simulation, Mentor Testkompress, Synopsys Tetramax, DFTMAX, JTAG, IEEE1500
Industry
Semiconductor Manufacturing